draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra UM10430 lpc18xx arm cortex-m3 microcontroller rev. 00.13 ? 20 july 2011 user manual document information info content keywords lpc18xx, lpc1850, lpc1830, lpc1 820, lpc1810, lpc1857, lpc1853, lpc1837, lpc1833, lpc1827, lpc18 25, lpc1823, lpc1822, lpc1817, lpc1815, lpc1813, lpc1812, lpc1 810, arm cortex-m3, spifi, sct, usb, ethernet abstract lpc18xx user manual describing rev ?-? and rev ?a? version of parts lpc1850/30/20/10 (flashless parts). a preliminary description of parts lpc1857/53/37/33/27/25/ 23/22/17/15/13/12 (flash-based parts) is included. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 2 of 1164 nxp semiconductors UM10430 lpc18xx user manual revision history rev date description 0.13 preliminary lpc18xx user manual. modifications: ? location of c_can1 reset updated in the rgu (see ta b l e 9 1 , ta b l e 9 3 , ta b l e 9 7 ). ? pin p2_7 replaced by pin p2_9 as boot pin in table 107 and ta b l e 8 . ? pin p2_7 designated as isp entry pin in table 107 . ? boot rom size increased to 64 kb. ? editorial updates. ? isp commands for flashless parts included in chapter 40 . 0.12 preliminary lpc18xx user manual. modifications: ? all content relating to lpc1850/30/20/10 rev ?-? moved to chapter 42 . ? repeater and plain input mode swapped in sfsp registers (see section 42.7.4.1 ). ? chapter 7 added. ? use of divide-by-two clock for emc added ( section 19.1 ). ? bit description of rit mask register updated ( table 608 ). ? overdrive mode removed in bits 1:0 of the pumucon register (see table 32 and ta b l e 9 1 8 ). 0.11 preliminary lpc18xx user manual. modifications: ? chapter 5 , chapter 6 , chapter 7 , chapter 14 , chapter 35 added. 0.10 preliminary lpc18xx user manual. modifications: ? chapter 14 , chapter 9 , chapter 13 , chapter 15 added. 0.09 preliminary lpc18xx user manual. modifications: ? register bit description and functional description removed in chapter 17 . api calls to be added. ? description of msgval bit updated in table 757 . ? mac_rwake_frflt register cannot used with bit-banding. see table 413 . ? description of rmii and mii pins corrected in table 401 . ? description of ethernet function in pins p1_16 and pc_8 updated. ? aes description removed chapter 4 ? lpc18xx security features ? . ? cgu pll0 output updated in table 107 . ? in ta b l e 1 7 5 , pin pc_0: change function 0 to n.c. and move enet_rx_clk to function 3. ? in ta b l e 1 7 5 , remove all sdio functions. ? in ta b l e 1 7 5 , change can1_rd, can1_td to can_rd, can_td. ? polarity of the enable bit updated in ta b l e 11 2 (1= power-down). ? wic replaced by event router throughout the manual. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 3 of 1164 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors UM10430 lpc18xx user manual 0.08 preliminary lpc18xx user manual. modifications: ? updated the reference clock for the frequency monitor register ( section 12.6.1 ). ? description of rtc calibration updated ( section 31.7.1 ). ? usb0 clock source description added to ta b l e 2 9 4 . ? usb1 clock source description added to ta b l e 3 5 8 . ? boot source bit 3 (pin p2_7) and usb0/1 boot modes added to ta b l e 7 and table 8 . ? add sram control register etbcfg in creg block ( ta b l e 3 6 ). ? rtc initialization steps updated ( section 31.2 ). ? access of lcd controller to sram updated ( section 23.7.1.1 and section 23.7.1.2 ). ? adc measurement range corrected ( section 38.3 ). ? gpdma, cxcontrol register: bits transfer size are given in number of transfers ( table 214 ). ? chapter 4 ? lpc18xx security features ? added. ? pin configuration updated ( table 175 ). ? flash parts added (see chapter 1 ? introductory information ? and chapter 2 ? lpc18xx memory mapping ? . ? chapter 40 ? lpc18xx flash programming interface ? added. 0.07 preliminary lpc18xx user manual. revision history ?continued rev date description www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 4 of 1164 1.1 introduction the lpc18xx are arm cortex-m3 based microcontrollers for embedded applications. the arm cortex-m3 is a next generation core that offers system enhancements such as low power consumption, enhanced debug feat ures, and a high level of support block integration. the lpc18xx operate at cpu frequencies of up to 150 mhz. the arm cortex-m3 cpu incorporates a 3-stage pipeline and uses a harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. the arm cortex-m3 cpu also includes an internal prefetch un it that supports speculative branching. the lpc18xx include up to 200 kb of on-chip sram data memory (flashless parts) or up to 136 kb of on-chip sram and up to 1 mb of flash (parts with on-chip flash), a quad spi flash interface (spifi), a state configurable timer (sct) subsystem, two high-speed usb controllers, ethernet, lcd, an external memory controller, and multiple digital and analog peripherals. remark: this user manual describes the rev ?-? and rev ?a? versions of parts lpc1850/30/20/10 (flashless parts) and pr ovides a preliminary description of the flash-based lpc18xx parts. the following peripherals are available on lpc1350/30/20/10 rev ?a? only: ? i2s1 ? c_can1 ? gpio pin interrupts ? gpio group interrupt 0/1 ? global input multiplexer array (gima) 1.2 features ? processor core ? arm cortex-m3 processor, running at frequencies of up to 150 mhz. ? arm cortex-m3 built-in memory protection unit (mpu) supporting eight regions. ? arm cortex-m3 built-in nested vect ored interrupt controller (nvic). ? non-maskable interrupt (nmi) input. ? jtag and serial wire debug, serial trace, eight breakpoints, and four watch points. ? etm and etb support. ? system tick timer. ? on-chip memory (flashless parts lpc1850/30/20/10) ? up to 200 kb sram total for code and data use. UM10430 chapter 1: introductory information rev. 00.13 ? 20 july 2011 user manual www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 5 of 1164 nxp semiconductors UM10430 chapter 1: introductory information ? two 32 kb sram blocks with separate bu s access. both sram blocks can be powered down individually. ? 64 kb rom containing boot code and on-chip software drivers. ? 32-bit one-time programmable (otp) memo ry for general-purpose customer use. ? on-chip memory (parts with on-chip flash) ? up to 1 mb total dual bank flas h memory with flash accelerator. ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. ? up to 136 kb sram for code and data use. ? two 32 kb sram blocks with separate bu s access. both sram blocks can be powered down individually. ? 32 kb rom containing boot code and on-chip software drivers. ? 32-bit one-time programmable (otp) memo ry for general-purpose customer use. ? clock generation unit ? crystal oscillator with an opera ting range of 1 mhz to 25 mhz. ? 12 mhz internal rc oscillato r trimmed to 1 % accuracy. ? ultra-low power rtc crystal oscillator. ? three plls allow cpu operation up to the maximum cpu rate without the need for a high-frequency crystal. the second pll is dedicated to the high-speed usb, the third pll can be used as audio pll. ? clock output. ? serial interfaces: ? quad spi flash interface (spi fi) with four lanes and data rates of up to 40 mb per second total. ? 10/100t ethernet mac with rmii and mii interfaces and dma support for high throughput at low cpu load. support for ieee 1588 time stamping/adva nced time stamping (ieee 1588-2008 v2). ? one high-speed usb 2.0 host/device/otg interface with dma support and on-chip phy. ? one high-speed usb 2.0 host/device interface with dma support, on-chip full-speed phy and ulpi interface to external high-speed phy. ? usb interface electrical test so ftware included in rom usb stack. ? four 550 uarts with dma support: one uart with full modem interface; one uart with irda interface; three usarts support synchronous mode and a smart card interface conforming to iso7816 specification. ? two c_can 2.0b controllers with one channel each. ? two ssp controllers with fifo and multi- protocol support. both ssps with dma support. ? one fast-mode plus i 2 c-bus interface with monitor mode and with open-drain i/o pins conforming to the full i 2 c-bus specification. supports data rates of up to 1 mbit/s. ? one standard i 2 c-bus interface with monitor mode and standard i/o pins. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 6 of 1164 nxp semiconductors UM10430 chapter 1: introductory information ? two i 2 s interfaces with dma support, each with one input and one output. ? digital peripherals: ? external memory controller (emc) support ing external sram, rom, nor flash, and sdram devices. ? lcd controller with dma support and a programmable display resolution of up to 1024h ? 768v. supports monochrome and color stn panels and tft color panels; supports 1/2/4/8 bpp clut an d 16/24-bit direct pixel mapping. ? sd/mmc card interface. ? eight-channel general-purpose dma (gpdma) controller can access all memories on the ahb and all dma-capable ahb slaves. ? up to 80 general-purpose input/outp ut (gpio) pins with configurable pull-up/pull-down resistors and open-drain modes. ? gpio registers are located on the ahb for fast access. gpio ports have dma support. ? state configurable timer (sct) subsystem on ahb. ? four general-pur pose timer/counters with ca pture and match capabilities. ? one motor control pwm for three-phase motor control. ? one quadrature encoder interface (qei). ? repetitive interrupt timer (ri timer). ? windowed watchdog timer. ? ultra-low power real-time clock (rtc) on separate power domain with 256 bytes of battery powered backup registers. ? alarm timer; can be battery powered. ? digital peripherals available on flash-based parts lpc18xx only: ? ? analog peripherals: ? one 10-bit dac with dma support and a data conversion rate of 400 ksamples/s. ? two 10-bit adcs with dma support and a data conversion rate of 400 ksamples/s. ? security: ? hardware-based aes security engine programmabl e through an on-chip api. ? two 128-bit secure otp memories fo r aes key storage an d customer use. ? unique id for each device. ? power: ? single 3.3 v (2.2 v to 3.6 v) power supply with on-chip internal voltage regulator for the core supply and the rtc power domain. ? rtc power domain can be powered separately by a 3 v battery supply. ? four reduced power modes: sleep, deep-sleep, power-down, and deep power-down. ? processor wake-up from sleep mode via wake-up interrupts from various peripherals. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 7 of 1164 nxp semiconductors UM10430 chapter 1: introductory information ? wake-up from deep-sleep, power-down, and deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the rtc power domain. ? brownout detect with four separate thre sholds for interrupt and forced reset. ? power-on reset (por). ? available as 100-pin, 144-pin, and 208-pin lqfp packages and as 100-pin, 180-pin, and 256-pin lbga packages. 1.3 ordering information (fl ashless parts lpc1850/30/20/10) table 1. ordering information type number package name description version lpc1850fet256 lbga256 plastic low profile ba ll grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 lpc1850fet180 tfbga180 thin fine-pitch ball grid array package; 180 balls sot570-3 lpc1850fbd208 lqfp208 plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm sot459-1 lpc1830fet256 lbga256 plastic low profile ba ll grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 lpc1830fet180 tfbga180 thin fine-pitch ball grid array package; 180 balls sot570-3 lpc1830fet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm sot926-1 lpc1830fbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm sot486-1 lpc1820fet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm sot926-1 lpc1820fbd144 lqfp144 plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm sot486-1 lpc1820fbd100 lqfp100 plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1 lpc1810fet100 tfbga100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm sot926-1 table 2. ordering options type number total sram lcd ethernet usb0 (host, device, otg) usb1 (host, device) gpio package lpc1850fet256 200 kb yes yes yes yes 164 lbga256 lpc1850fet180 200 kb yes yes yes yes 118 tfbga180 lpc1850fbd208 200 kb yes yes yes yes 164 lqfp208 lpc1830fet256 200 kb no yes yes yes 164 lbga256 lpc1830fet180 200 kb no yes yes yes 118 tfbga180 lpc1830fet100 200 kb no yes yes yes 49 tfbga100 lpc1830fbd144 200 kb no yes yes yes 83 lqfp144 lpc1820fet100 168 kb no no yes no 49 tfbga100 lpc1820fbd144 168 kb no no yes no 83 lqfp144 lpc1820fbd100 168 kb no no yes no 49 lqfp100 lpc1810fet100 136 kb no no no no 49 tfbga100 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 8 of 1164 nxp semiconductors UM10430 chapter 1: introductory information 1.4 ordering information (parts with on-chip flash) table 3. ordering information (parts with on-chip flash) type number package name description version lpc1857fet256 lbga256 plastic low profile ba ll grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 lpc1857 lqfp208 lpc1857 bga180 lpc1837fet256 lbga256 plastic low profile ba ll grid array package; 256 balls; body 17 ? 17 ? 1 mm sot740-2 lpc1837 lqfp208 lpc1837 bga180 lpc1827 lqfp144 lpc1827fet100 bga100 lpc1825 lqfp144 lpc1825fet100 bga100 lpc1823 lqfp144 lpc1823fet100 bga100 lpc1822 lqfp144 lpc1822fet100 bga100 lpc1817 lqfp144 lpc1817fet100 bga100 lpc1815 lqfp144 lpc1815fet100 bga100 lpc1813 lqfp144 lpc1813fet100 bga100 lpc1811 lqfp144 lpc1811fet100 bga100 table 4. ordering options (parts with on-chip flash) type sram total flash total flash bank a flash bank b lcd ethernet usb0 (host, device, otg) usb1 (host, device) packages lpc1857 136 kb 1 mb 512 kb 512 kb yes yes yes yes lbga256; bga180; lqfp208 lpc1853 136 kb 512 kb 256 kb 256 kb yes yes yes yes lbga256; bga180; lqfp208 lpc1837 136 kb 1 mb 512 kb 512 kb no yes yes yes lbga256; bga180; lqfp208 lpc1833 136 kb 512 kb 256 kb 256 kb no yes yes yes lbga256; bga180; lqfp208 lpc1827 136 kb 1 mb 512 kb 512 kb no no yes no lqfp144; bga100 lpc1825 136 kb 768 kb 384 kb 384 kb no no yes no lqfp144; bga100 lpc1823 104 kb 512 kb 256 kb 256 kb no no yes no lqfp144; bga100 lpc1822 104 kb 512 kb 512 kb 0 no no yes no lqfp144; bga100 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 9 of 1164 nxp semiconductors UM10430 chapter 1: introductory information lpc1817 136 kb 1 mb 512 kb 512 kb no no no no lqfp144; bga100 lpc1815 136 kb 768 kb 384 kb 384 kb no no no no lqfp144; bga100 lpc1813 104 kb 512 kb 256 kb 256 kb no no no no lqfp144; bga100 lpc1812 104 kb 512 kb 512 kb 0 no no no no lqfp144; bga100 table 4. ordering options (parts with on-chip flash) type sram total flash total flash bank a flash bank b lcd ethernet usb0 (host, device, otg) usb1 (host, device) packages www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 10 of 1164 nxp semiconductors UM10430 chapter 1: introductory information 1.5 block diagram (flashle ss parts lpc1850/30/20/10) fig 1. lpc18xx block diagram (flashless parts) arm cortex-m3 test/debug interface i-code bus d-code bus system bus swd/trace port/jtag gpdma ethernet (1) 10/100 mac ieee 1588 usb1 (1) host/ device high- speed usb0 (1) host/ device/ otg lcd (1) sd/ mmc emc high-speed phy 16/32 kb ahb sram 16 kb + 16 kb ahb sram (1) spifi aes hs gpio sct 64 kb rom ahb multilayer matrix lpc1850/30/20/10 64/96 kb local sram 40 kb local sram 002aaf218 slaves masters wwdt usart0 uart1 ssp0 i 2 c0 c_can1 i 2 s0 i 2 s1 motor control pwm (1) timer3 timer2 usart2 usart3 ssp1 ri timer qei (1) gima bridge 0 bridge 1 bridge 2 bridge 3 bridge 10-bit adc0 10-bit adc1 c_can0 i 2 c1 10-bit dac bridge rgu ccu2 cgu ccu1 alarm timer configuration registers otp memory event router power mode control 12 mhz irc rtc power domain backup registers rtc osc rtc slaves = connected to gpdma timer0 timer1 scu gpio interrupts gpio group0 interrupt gpio group1 interrupt www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 11 of 1164 nxp semiconductors UM10430 chapter 1: introductory information fig 2. lpc18xx ahb multilayer matrix connections (flashless parts) arm cortex-m3 test/debug interface gpdma ethernet (1) usb1 (1) usb0 (1) lcd (1) sd/ mmc slaves 64 kb rom 64/96 kb local sram 40 kb local sram tem bus i-code bus d-code bus masters 01 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 12 of 1164 nxp semiconductors UM10430 chapter 1: introductory information 1.6 block diagram (parts with on-chip flash) (1) not available on all parts (see ta b l e 4 ). fig 3. lpc185x/3x/2x/1x block diagram (parts with on-chip flash) arm cortex-m3 test/debug interface i-code bus d-code bus system bus swd/trace port/jtag gpdma ethernet (1) 10/100 mac ieee 1588 usb1 (1) host/ device high- speed usb0 (1) host/ device/ otg lcd (1) sd/ mmc (1) high-speed phy ahb multilayer matrix lpc185x/3x/2x/1x slaves masters wwdt usart0 uart1 ssp0 i 2 c0 i 2 s0 motor control pwm timer3 timer2 usart2 usart3 ssp1 ri timer qei bridge 0 bridge 1 bridge 2 bridge 3 bridge 10-bit adc0 10-bit adc1 c_can0 i 2 c1 10-bit dac bridge rgu ccu2 cgu ccu1 alarm timer configuration registers otp memory event router power mode control 12 mhz irc rtc power domain backup registers rtc osc rtc slaves = connected to gpdma timer0 timer1 scu emc 32 kb ahb sram 16 +16 kb ahb sram spifi aes hs gpio spi sgpio sct 32 kb rom 32 kb local sram (1) 40 kb local sram 512 kb flash (1) 512 kb flash (1) c_can1 i 2 s1 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 13 of 1164 nxp semiconductors UM10430 chapter 1: introductory information (1) not available on all parts (see ta b l e 4 ). fig 4. ahb multilayer matrix master and slave connections arm cortex-m3 test/debug interface gpdma ethernet (1) usb1 (1) usb0 (1) lcd (1) sd/ mmc (1) external memory controller ahb register interfaces, apb, rtc domain peripherals 32 kb ahb sram 16 kb + 16 kb ahb sram slaves 32 kb rom 32 kb local sram (1) 40 kb local sram system bus i-code bus d-code bus masters 01 ahb multilayer matrix = master-slave connection 512 kb flash (1) 512 kb flash (1) www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 14 of 1164 2.1 how to read this chapter the available peripherals and their memories vary for different parts. ? ethernet: available on lpc185x/3x. ? usb0: available on lpc185x/3x/2x. ? usb1: available on lpc185x/3x. ? sram: see ta b l e 5 . ? flash: see ta b l e 6 . the registers and memory regions correspondi ng to unavailable peripheral and memory blocks are reserved. the following memory blocks are available on lpc1350/30/20/10 rev ?a? only: ? i2s1 at address 0x400a 3000. ? c_can1 at address 0x400a 4000. ? gpio pin interrupts 0x4008 7000. ? gpio group interrupt 0/1 at addresses 0x4008 8000 and 0x4008 9000. ? high-speed gpio at address 0x400f 4000 (on parts lpc1850/30/20/10 rev ?-? parts, the gpio block resides at address 0x400f 0000). ? global input multiplexer array (gima) at address 0x400c 7000. 2.2 basic configuration in the creg block (see ta b l e 3 6 ), select the interface to ac cess the 16 kb block of ram located at address 0x2000 c000. this ram memory block can be accessed either by the etb (this is the default) or be used as normal sram on the ahb bus. 2.3 memory configuration 2.3.1 on-chip static ram the lpc18xx support up to 136 kb sram (parts with on-chip flash) or up to 200 kb sram (flashless parts lpc1850/30/20/10) with separate bus master access for higher throughput and individual power control for low power operation. UM10430 chapter 2: lpc18xx memory mapping rev. 00.13 ? 20 july 2011 user manual www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 15 of 1164 nxp semiconductors UM10430 chapter 2: lpc18xx memory mapping 2.3.2 on-chip flash the available flash configuration for the lpc185x/3x/2x/1x is shown in ta b l e 6 . a flash accelerator maximizes performance fo r use with the two fast ahb buses. table 5. lpc185x/3x/2x/1x sram configuration part local sram local sram local sram local sram ahb sram ahb sram ahb sram 0x1000 0000 0x1001 0000 0x1008 0000 0x1008 8000 0x2000 0000 0x2000 8000 0x2000 c000 lpc1850 64 kb 32 kb 32 kb 8 kb 32 kb 16 kb 16 kb figure 5 lpc1830 64 kb 32 kb 32 kb 8 kb 32 kb 16 kb 16 kb figure 5 lpc1820 64 kb 32 kb 32 kb 8 kb 16 kb - 16 kb figure 5 lpc1810 64 kb - 32 kb 8 kb 16 kb - 16 kb figure 5 lpc1857 figure 7 lpc1853 figure 7 lpc1837 figure 7 lpc1833 figure 7 lpc1827 figure 7 lpc1825 figure 7 lpc1823 figure 7 lpc1822 figure 7 lpc1817 figure 7 lpc1815 figure 7 lpc1813 figure 7 lpc1812 figure 7 table 6. lpc185x/3x/2x/1x flash configuration part flash bank a 256 kb flash bank a 128 kb flash bank a 128 kb flash bank b 256 kb flash bank b 128 kb flash bank b 128 kb 0x1a00 0000 0x1a04 000 0x1a0 6000 0x1b00 0000 0x1b04 000 0x1b0 6000 lpc1857 yes yes yes yes yes yes lpc1853 yes no no yes no no lpc1837 yes yes yes yes yes yes lpc1833 yes no no yes no no lpc1827 yes yes yes yes yes yes lpc1825 yes yes no yes yes no lpc1823 yes no no yes no no lpc1822 yes yes yes no no no lpc1817 yes yes yes yes yes yes www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 16 of 1164 nxp semiconductors UM10430 chapter 2: lpc18xx memory mapping 2.3.3 bit banding remark: bit banding can not be used with the mac_rwake_frflt register (see section 22.6.10 ). 2.4 general description lpc1815 yes yes no yes yes no lpc1813 yes no no yes no no lpc1812 yes yes yes no no no table 6. lpc185x/3x/2x/1x flash configuration part flash bank a 256 kb flash bank a 128 kb flash bank a 128 kb flash bank b 256 kb flash bank b 128 kb flash bank b 128 kb 0x1a00 0000 0x1a04 000 0x1a0 6000 0x1b00 0000 0x1b04 000 0x1b0 6000 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 17 of 1164 nxp semiconductors UM10430 chapter 2: lpc18xx memory mapping 2.5 memory map (flashless parts lpc1850/30/20/10) fig 5. system memory map - flashless parts lpc1850/30/20/10 (see figure 6 for detailed addresses of all peripherals) reserved peripheral bit band alias region reserved high-speed gpio reserved 0x0000 0000 0 gb 1 gb 4 gb 0x2001 0000 0x2200 0000 0x2400 0000 0x2800 0000 0x1000 0000 0x3000 0000 0x4000 0000 0x4001 2000 0x4004 0000 0x4005 0000 0x4010 0000 0x4400 0000 0x6000 0000 ahb peripherals apb peripherals #0 apb peripherals #1 reserved reserved reserved rtc domain peripherals 0x4006 0000 0x4008 0000 0x4009 0000 0x400a 0000 0x400b 0000 0x400c 0000 0x400d 0000 0x400e 0000 0x400f 0000 0x400f 1000 0x400f 2000 0x400f 4000 0x400f 8000 clocking/reset peripherals apb peripherals #2 apb peripherals #3 0x2000 8000 16 kb ahb sram (lpc1850/30) 16 kb ahb sram (lpc1850/30/20/10) 0x2000 c000 16 kb ahb sram (lpc1850/30) 16 kb ahb sram (lpc1850/30/20/10) reserved reserved aes 0x4010 1000 0x4010 2000 0x4200 0000 reserved local sram/ external static memory banks 0x2000 0000 0x2000 4000 128 mb dynamic external memory dycs0 256 mb dynamic external memory dycs1 256 mb dynamic external memory dycs2 256 mb dynamic external memory dycs3 0x7000 0000 0x8000 0000 0x8800 0000 0xe000 0000 256 mb shadow area 1000 0000 1001 8000 1008 0000 008 a000 1040 0000 1041 0000 c00 0000 d00 0000 reserved reserved 32 mb ahb sram bit banding reserved reserved reserved 0xe010 0000 0xffff ffff reserved spifi data arm private bus reserved 1001 0000 32 kb local sram (lpc1850/30/20) 64 kb local sram (lpc1850/30/20/10) 32 kb + 8 kb local sram (lpc1850/30/20/10) reserved reserved reserved reserved 64 kb rom e00 0000 f00 0000 2000 0000 16 mb static external memory cs3 16 mb static external memory cs2 16 mb static external memory cs1 16 mb static external memory cs0 1400 0000 1800 0000 64 mb spifi data 002aaf228 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 18 of 1164 nxp semiconductors UM10430 chapter 2: lpc18xx memory mapping fig 6. memory map with peripherals - flashless parts lpc1850/30/20/10 (see figure 5 for detailed addresses of memory blocks) reserved peripheral bit band alias region high-speed gpio reserved reserved reserved 0x4000 0000 0x0000 0000 0x4001 2000 0x4004 0000 0x4005 0000 0x4010 0000 0x4400 0000 0x6000 0000 0xffff ffff ahb peripherals sram memories external memory banks apb0 peripherals apb1 peripherals reserved reserved reserved rtc domain peripherals 0x4006 0000 0x4008 0000 0x4009 0000 0x400a 0000 0x400b 0000 0x400c 0000 0x400d 0000 0x400e 0000 0x400f 0000 0x400f 1000 0x400f 2000 0x400f 4000 0x400f 8000 clocking/reset peripherals apb2 peripherals apb3 peripherals reserved reserved aes 0x4010 1000 0x4010 2000 0x4200 0000 reserved external memories and arm private bus apb2 peripherals 0x400c 1000 0x400c 2000 0x400c 3000 0x400c 4000 0x400c 6000 0x400c 8000 0x400c 7000 0x400c 5000 0x400c 0000 ri timer usart2 usart3 timer2 timer3 ssp1 qei apb1 peripherals 0x400a 1000 0x400a 2000 0x400a 3000 0x400a 4000 0x400a 5000 0x400b 0000 0x400a 0000 motor control pwm i2c0 i2s0 i2s1 c_can1 reserved ahb peripherals 0x4000 1000 0x4000 0000 sct 0x4000 2000 0x4000 3000 0x4000 4000 0x4000 6000 0x4000 8000 0x4001 0000 0x4001 2000 0x4000 9000 0x4000 7000 0x4000 5000 dma sd/mmc emc usb1 lcd usb0 reserved spifi ethernet reserved 0x4008 1000 0x4008 0000 wwdt 0x4008 2000 0x4008 3000 0x4008 4000 0x4008 6000 0x4008 a000 0x4008 7000 0x4008 8000 0x4008 9000 0x4008 5000 uart1 w/ modem ssp0 timer0 timer1 scu gpio interrupts gpio group0 interrupt gpio group1 interrupt usart0 rtc domain peripherals 0x4004 1000 0x4004 0000 alarm timer 0x4004 2000 0x4004 3000 0x4004 4000 0x4004 6000 0x4004 7000 0x4004 5000 power mode control creg event router otp controller reserved reserved rtc backup registers clocking reset control peripherals 0x4005 1000 0x4005 0000 cgu 0x4005 2000 0x4005 3000 0x4005 4000 0x4006 0000 ccu2 rgu ccu1 lpc1850/30/20/10 002aaf229 reserved reserved apb3 peripherals 0x400e 1000 0x400e 2000 0x400e 3000 0x400e 4000 0x400f 0000 0x400e 5000 0x400e 0000 i2c1 dac c_can0 adc0 adc1 reserved gima apb0 peripherals www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 19 of 1164 nxp semiconductors UM10430 chapter 2: lpc18xx memory mapping 2.6 memory map (parts with on-chip flash) (1) not available on all parts (see ta b l e 4 ). fig 7. system memory map - part s with on-chip flash (overview) reserved peripheral bit band alias region reserved 0x0000 0000 0 gb 1 gb 4 gb 0x2001 0000 0x2200 0000 0x2400 0000 0x2800 0000 0x1000 0000 0x3000 0000 0x4000 0000 0x4001 2000 0x4004 0000 0x4005 0000 0x4010 0000 0x4400 0000 0x6000 0000 ahb peripherals apb peripherals #0 apb peripherals #1 reserved reserved reserved rtc domain peripherals 0x4006 0000 0x4008 0000 0x4009 0000 0x400a 0000 0x400b 0000 0x400c 0000 0x400d 0000 0x400e 0000 0x400f 0000 0x400f 1000 0x400f 2000 clocking/reset peripherals apb peripherals #2 apb peripherals #3 0x2000 8000 16 kb ahb sram 16 kb ahb sram 0x2000 c000 16 kb ahb sram 16 kb ahb sram high-speed gpio reserved reserved aes 0x4010 1000 0x4010 2000 0x4200 0000 reserved local sram/dual flash banks/ external static memory banks 0x2000 0000 0x2000 4000 128 mb dynamic external memory dycs0 256 mb dynamic external memory dycs1 256 mb dynamic external memory dycs2 256 mb dynamic external memory dycs3 0x7000 0000 0x8000 0000 0x8800 0000 0xe000 0000 256 mb shadow area lpc185x/3x/2x/1x reserved reserved 32 mb ahb sram bit banding reserved reserved 0xe010 0000 0xffff ffff reserved spifi data arm private bus reserved 002aaf228wflash 0x1000 0000 0x1000 8000 0x1008 0000 0x1008 a000 0x1040 0000 0x1040 8000 0x1c00 0000 0x1d00 0000 32 kb local sram (1) 32 kb + 8 kb local sram reserved reserved reserved reserved reserved 32 kb rom 0x1e00 0000 0x1f00 0000 0x2000 0000 16 mb static external memory cs3 16 mb static external memory cs2 16 mb static external memory cs1 16 mb static external memory cs0 0x1a00 0000 0x1a04 0000 0x1a06 0000 0x1a08 0000 256 kb flash bank a 128 kb flash bank a 128 kb flash bank a 0x1b00 0000 0x1b08 0000 0x1b04 0000 0x1b06 0000 256 kb flash bank b 128 kb flash bank b 128 kb flash bank b www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 20 of 1164 nxp semiconductors UM10430 chapter 2: lpc18xx memory mapping (1) not available on all parts (see ta b l e 4 ). fig 8. memory mapping - parts wi th on-chip flas h (peripherals) reserved peripheral bit band alias region reserved 0x4000 0000 0x0000 0000 0x4001 2000 0x4004 0000 0x4005 0000 0x4010 0000 0x4400 0000 0x6000 0000 0xffff ffff ahb peripherals sram memories external memory banks apb peripherals #0 apb peripherals #1 reserved reserved reserved rtc domain peripherals 0x4006 0000 0x4008 0000 0x4009 0000 0x400a 0000 0x400b 0000 0x400c 0000 0x400d 0000 0x400e 0000 0x400f 0000 0x400f 1000 0x400f 2000 clocking/reset peripherals apb peripherals #2 apb peripherals #3 high-speed gpio reserved reserved aes 0x4010 1000 0x4010 2000 0x4200 0000 reserved external memories and arm private bus apb2 peripherals apb1 peripherals ahb peripherals 0x4000 1000 0x4000 0000 sct 0x4000 2000 0x4000 3000 0x4000 4000 0x4000 6000 0x4000 8000 0x4001 0000 0x4001 2000 0x4000 9000 0x4000 7000 0x4000 5000 dma sd/mmc (1) emc usb1 (1) lcd (1) usb0 (1) reserved spifi ethernet (1) reserved apb0 peripherals rtc domain peripherals 0x4004 1000 0x4004 0000 alarm timer 0x4004 2000 0x4004 3000 0x4004 4000 0x4004 6000 0x4004 7000 0x4004 5000 power mode control creg event router otp controller reserved reserved rtc backup registers clocking and reset control peripherals 0x4005 1000 0x4005 0000 cgu 0x4005 2000 0x4005 3000 0x4005 4000 0x4006 0000 ccu2 rgu ccu1 lpc185x/3x/2x/1x 002aaf229wflash reserved reserved apb3 peripherals 0x400c 1000 0x400c 2000 0x400c 3000 0x400c 4000 0x400c 6000 0x400d 0000 0x400c 7000 0x400c 5000 0x400c 0000 ri timer usart2 usart3 timer2 timer3 ssp1 qei 0x400a 1000 0x400a 2000 0x400a 3000 0x400a 4000 0x400a 5000 0x400b 0000 0x400a 0000 motor control pwm i2c0 i2s0 i2s1 c_can1 reserved 0x4008 1000 0x4008 0000 wwdt 0x4008 2000 0x4008 3000 0x4008 4000 0x4008 6000 0x4009 0000 0x4008 7000 0x4008 5000 uart1 w/ modem ssp0 timer0 timer1 scu reserved usart0 0x400e 1000 0x400e 2000 0x400e 3000 0x400e 4000 0x400f 0000 0x400e 5000 0x400e 0000 i2c1 dac c_can0 adc0 adc1 reserved reserved www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 21 of 1164 nxp semiconductors UM10430 chapter 2: lpc18xx memory mapping www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 22 of 1164 3.1 how to read this chapter this chapter applies to flashless parts lpc1850/30/20/10 only. 3.2 features the boot rom memory includes the following features: ? rom memory size is 64 kb. ? supports booting from uart interfaces and external static memory such as nor flash, spi flash, quad spi flash. ? includes apis for power control and otp programming. ? includes spifi and usb drivers. ? isp mode for loading data to on-chip sr am and execute code from on-chip sram. aes capable parts also support: ? cmac authentication on the boot image. ? secure booting from an encrypted image. ? supports development mode for booting from a plain text image. development mode is terminated by programming the aes key. ? api for aes programming. 3.3 functional description the internal rom memory is used to stor e the boot code. after a reset, the arm processor will start its code ex ecution from this memory. the arm core is configured to start executin g code, upon reset, with the program counter being set to the value 0x0000 0000. the lpc1 8xx contains a shadow pointer that allows areas of memory to be mapped to address 0x0000 0000. the default value of the shadow pointer is 0x1040 0000, ensuring that the code contained in the boot rom is executed at reset. several boot modes are available depending on the values of the otp bits boot_src. if the otp memory is not programmed or the boot_src bits are all zero, the boot mode is determined by the states of the bo ot pins p2_8, p2_8, p1_2, and p1_1. UM10430 chapter 3: lpc18xx boot rom rev. 00.13 ? 20 july 2011 user manual www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 23 of 1164 nxp semiconductors UM10430 chapter 3: lpc18xx boot rom [1] the boot loader programs the appropriate pin functi on at reset to boot using either ssp0 or spifi. [1] the boot loader programs the appropriate pin functi on at reset to boot using either ssp0 or spifi. table 7. boot mode when otp boot_src bits are programmed boot mode boot_src bit 3 boot_src bit 2 boot_src bit 1 boot_src bit 0 description boot pins 0 0 0 0 boot source is defined by the reset state of p1_1, p1_2, and p2_8 pins. see ta b l e 8 . uart 0 0 0 1 boot from device connected to usart0 using pins p2_0 and p2_1. spifi 0 0 1 0 boot from quad spi fl ash connected to the spifi interface using pins p3_3 to p3_8. emc 8-bit 0 0 1 1 boot from external static memory (such as nor flash) using cs0 and an 8-bit data bus. emc 16-bit 0 1 0 0 boot from external static memory (such as nor flash) using cs0 and a 16-bit data bus. emc 32-bit 0 1 0 1 boot from external static memory (such as nor flash) using cs0 and a 32-bit data bus. usb0011 0boot from usb0. usb1011 1boot from usb1. spi (ssp) 1 0 0 0 boot from spi fl ash connected to the ssp0 interface on p3_3, p3_6, p3_7 and p3_8 [1] . usart3 1 0 0 1 boot from device connected to usart3 using pins p2_3 and p2_4. table 8. boot mode when opt boot_src bits are zero boot mode p2_9 p2_8 p1_2 p1_1 description usart0 low low low low boot from device con nected to usart0 using pins p2_0 and p2_1. spifi low low low high boot from quad spi flas h connected to the spifi interface on p3_3 to p3_8 [1] . emc 8-bit low low high low boot from external st atic memory (such as nor flash) using cs0 and an 8-bit data bus. emc 16-bit low low high high boot fr om external static memory (such as nor flash) using cs0 and a 16-bit data bus. emc 32-bit low high low low boot from external st atic memory (such as nor flash) using cs0 and a 32-bit data bus. usb0 low high low high boot from usb0. usb1 low high high low boot from usb1. spi (ssp) low high high high boot from spi flas h connected to the ssp0 interface on p3_3, p3_6, p3_7 and p3_8 [1] . usart3 high low low low boot fr om device connected to usart3 using pins p2_3 and p2_4. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 24 of 1164 nxp semiconductors UM10430 chapter 3: lpc18xx boot rom 3.3.1 aes capable devices aes capable products will normally always boot from a secure (encry pted) image and use cmac authentication. however a special development mode allows booting from a plain text image. this developm ent mode is active when the aes key has not been programmed. in this case the aes key consists of all zeros. once the key is programmed (to a non-zero value), the development mode is terminated. 3.3.2 boot process the top level boot proc ess is illustrated in figure 9 . the boot starts after reset is released. the irc is selected as cpu clock and the cortex-m3 starts by executing boot rom. by default the jtag access to the chip is disabled at reset. when the part is non-aes capable or it is aes capable but the aes key has not been programmed then jtag access is enabled. as shown in figure 9 , the boot rom determines the boot mode based on the otp boot_src value or reset state of the pins p1_1, p1_2, p2_8, and p2_9. the boot rom copies the image to internal sram at location 0x1000 0000 and jumps to that location (sets arm's shadow pointer to 0x1000 0000) after image verification. hence the images for lpc18xx should be compiled with entry point at 0x0000 0000. on aes capable lpc18xx with a programmed aes key the image and header are authen ticated using the cmac algorithm. if authenticat ion fails the device is reset. on aes capable lpc18xx in development mode and non-aes capa ble lpc18xx, the image and header are not authenticated. if the image is not preceded by a header then the image is not copied to sram but assumed to be executable as-is. in that case the shadow pointer is set to t he first address location of the external boot memory. the header-less images for lpc18xx should be compiled with entry point at 0x0000 0000, the same as for an image with header. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 25 of 1164 nxp semiconductors UM10430 chapter 3: lpc18xx boot rom fig 9. boot process 4 of lpc 18 xx reset disable irq & mpu cpu clock = irc 12 mhz check boot _ src aes capable and key > 0 ? load aes key yes uart 0 boot spifi boot check pins p 2 _ 9 , p 2 _ 8 , p 1 _ 2 , p 1 _ 1 = 0 = 0 emc 8 b boot emc 32 b boot emc 16 b boot = 1 > 10 enable jtag no valid header ? yes no aes capable and cmac active ? yes copy image to sram and calculate cmac tag valid tag ? decrypt image in sram yes set shadow pointer = 0 x 1000 0000 development mode ? yes no copy image to sram reset no = 1 .. 4 , 7 cpu clock = pll 1 96 mhz read header read header = 2 .. 5 , 8 > 9 set shadow pointer = 0 x 1000 0000 set shadow pointer = boot address no spi boot uart 3 boot = 6 .. 7 , 9 usb 1 boot usb 2 boot boot _ src = 6 or pins = 5 boot _ src = 7 or pins = 6 boot _ src = 9 or pins = 8 boot _ src = 8 or pins = 7 boot _ src = 2 or pins = 1 boot _ src = 3 or pins = 2 boot _ src = 4 or pins = 3 boot _ src = 5 or pins = 4 boot _ src = 1 or pins = 0 valid header ? yes no 60 s timeout toggle pin p 1 _ 1 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 26 of 1164 nxp semiconductors UM10430 chapter 3: lpc18xx boot rom 3.3.3 boot image format aes capable products with a programmed aes ke y will always boot fr om a secure image and use cmac authentication. a secure image should always include a header. non-aes capable products may bo ot from an image with header or execute directly from the boot source (when the boot source is memory mapped; spifi or emc). when no valid header is found t hen the cpu will try to execute code from the first location of the memory mapped boot source. the user should take ca re that this location contains executable code, otherwise a hard fault exception will occu r. this exception jumps to a while(1) loop. the image must be preceded by a header that has the layout described in ta b l e 9 . non-encrypted images may omit the header. [1] can only be active if device is aes capable, else is considered an invalid image. [2] 16 extra bytes are required for the header bytes. [3] the image size should be set to no more than the size of the sram located at 0x1000 0000. table 9. image header address name description size [bits] 5:0 aes_active [1] aes encryption active 0x25 (100101): aes en cryption active 0x1a (011010): aes encryption not active else: invalid image 6 7:6 hash_active [1] indicates whether a hash is used: 00: cmac hash is used, value is hash_value 01: reserved 10: reserved 11: no hash is used 2 13:8 reserved 11...11 (binary) 6 15:14 aes_control these 2 bits can be set to a value such that when aes encryption is active, that the aes_active field, after aes encryption, is not equal to the value 0x1a (aes encryption not active) 2 31:16 hash_size [3] size of the part of t he image over which the hash value is calculated in number of 512 byte frames. also size of image copied to internal sram at boot time. hash size = 16 [2] + hash_size x 512 byte. 16 95:32 hash_value cmac hash value calculated over the first bytes of the image (starting right from the header) as indicated by hash_size. the value is truncated to the 64 msb. 64 127:96 reserved 11...11 (binary) 32 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 27 of 1164 nxp semiconductors UM10430 chapter 3: lpc18xx boot rom 3.3.4 boot image creation 3.3.4.1 cmac the cmac algorithm is used to calculate a tag which is used for image authentication. the tag is stored in the header field hash_value. the authentication process is as follows: 1. use the cmac algorithm to generate the 128-bit tag. truncate the tag to 64 msb and insert this truncated tag in the header. 2. at boot time the tag is recalculated. au thentication passes when the calculated tag is equal to the received tag in the image header. to generate an l-bit cmac tag t of mess age m using a 128-bit block cipher aes and secret key k, the cmac tag generation process is as follows: 1. generate sub key k 1 : ? calculate a temporary value k 0 = aes k (0). ? if msb(k 0 ) = 0 then k 1 = (k 0 << 1) else k 1 = (k 0 << 1) ? 0x87 2. divide message into 128-bit blocks m = m 1 || ... || m n-1 || m n *, where m 1 ...m n-1 are complete blocks. 3. the last block, m n *, should be padded to be a complete block and then m n = k 1 ? m n *. 4. let c 0 = 00...0. 5. for i = 1, ..., n, calculate c i = aes k (c i-1 ? m i ). 6. output t = msb l (c n ). the first message block is the header. since the cmac tag is stored in the header field hash_value, and this tag is not yet known until after cmac calculation, a temporary header with a dummy tag value of 0x3456789a is used during cmac calculation. this dummy value should be replaced by the calc ulated tag value in the final header field hash_value. for lpc18xx the chosen cmac parameters are: encryption key k = user key (same as used for decryption) and tag length l = 64. data is processed in little endian mode. this means that the first byte read from the image is integrat ed into the aes codeword as least significant byte. the 16th byte read from the image is the most significant byte of the first aes codeword. cmac is calculated over the header and encrypted image. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 28 of 1164 nxp semiconductors UM10430 chapter 3: lpc18xx boot rom 3.3.4.2 uart boot mode figure 11 details the boot-flow steps of the uart boot mode. the execution of this mode happens only if the boot mode is set accordingly (see boot modes ta b l e 7 and ta b l e 8 ). as illustrated in figure 11 , configure the uart with the following settings: ? baudrate = 115200 (uart divisor registers are programmed assuming a 12 mhz clock frequency). ? data bits = 8. ? parity = none. ? stop bits = 1. auto baud is active; boot waits until 0x3f is received and responds with ?ok?. this should be followed by the header and image. the boot rom doesn't implement any flow control or any handshake mechanisms during file transfer. fig 10. cmac generation m 1 aes k + m 2 aes k + m* n aes k k 1 msb 64 tag www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 29 of 1164 nxp semiconductors UM10430 chapter 3: lpc18xx boot rom 3.3.4.3 spifi boot mode figure 12 details the boot-flow steps of the quad spi flash boot mode . the execution of this mode happens only if the boot mo de is set accordingly (see boot modes table 7 and ta b l e 8 ). the spifi clock is 36 mhz. boot rom to support a spi flash boot, th e device should support ?high frequency continuous array read? (command 0x0b). since the boot rom doesn't rely on a response for commands 0xab, 0xb9 and 0x9f, as long as the spi device ignores or responds correctly to these command s, the lpc18xx will be able to boot from them. fig 11. uart boot process init uart assuming ffast_in =12mhz 1152000-8-n-1 setup pin configuration uart0 p2_1, p2_0 see main boot flow char = 0x3f? receive character no transmit ok yes www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 30 of 1164 nxp semiconductors UM10430 chapter 3: lpc18xx boot rom 3.3.4.4 emc boot modes the emc boot process follows the main flow shown in figure 13 . tthe cpu clock is set to 72 mhz, and a non-aes capable lpc18xx will boot directly from emc when the image does not contain a header. the emc uses 8 wait states. note that the number of address bits se lected in pin configuration is initially extbus_a[13:0]. after reading the header the address bits are extended to be in line with the image size as defined by hash_size, e.g. if hash_size is 100 kb then pins extbus_a[16:14] are configured since 2 17 > 100 kb. when booting without header then the image should configure extra address pins beyond the initially configured extbus_a[13:0]. fig 12. spifi boot process setup pin configuration p3_3..p3_8 read vendor_id supported vendor_id? activate vendor_id specific driver yes see main boot flow setup clock spifi_sck= 36mhz if sqi device supported then 4-bit i/o w ill be used no reset fig 13. emc boot process setup pin configuration extbus_a[13:0] extbus_cs0 read image header image size > 16384-16 extend address bus yes no see main boot flow www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 31 of 1164 nxp semiconductors UM10430 chapter 3: lpc18xx boot rom 3.3.4.5 spi boot mode the boot uses ssp0 in spi mo de. the spi clock is 18 mhz. figure 14 details the boot-flow steps of the spi flash boot mode. the execution of this mode happens only if the boot mode is set accordingly (see boot modes ta b l e 7 and ta b l e 8 ). 3.3.5 boot process timimg the following paramters describe the timing of the boot process: fig 14. spi boot process setup pin configuration p3_3, p3_6..p3_8 see main boot flow setup clock ssp0_sck= 18mhz table 10. boot process timing parameters parameter description value t_a check boot selection pins < 1 ? s t_b initialize device 250 ? s t_c copy image to embedded sram if part is executing from external flash with no copy < 0.3 ? s if the image is encrypted or must be copied < 1 ? s to 10000 ? s depending on the size of the image and the speed of the boot memory www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 32 of 1164 nxp semiconductors UM10430 chapter 3: lpc18xx boot rom 3.3.6 isp in-system programming (isp) is programming or re-programming the on-chip sram memory, using the boot loader software and the usart0 serial port. this can be done when the part resides in the end-user board. isp allows to load data into on-chip sram and execute code from on-chip sram. for details, see chapter 40 . fig 15. boot process timing gnd vddreg irc12 reset supply ramp up irc12 starts irc12 stable 22 s 0 .5 s; irc stability count valid threshold boot time user code processor status t a s t b s t c s check boot selection pins copy image to embedded sram initialise device www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 33 of 1164 4.1 how to read this chapter all lpc18xx parts support aes decoding. 4.2 features ? decoding of external image data. ? secure storage of decoding keys. ? support for cmac hash calcul ation to authenticate data. ? aes engine performance of 1 byte/clock cycle. ? aes engine supports: ? ecb decode mode with 128-bit key. ? cbc decode mode with 128-bit key. ? cmac hash calculation. 4.3 general description the lpc18xx uses an external image to stor e instruction code and data. if customers want to protect the external image content, then the lpc18xx offers hardware to accelerate processing for data decoding, data integrity and proof of origin. the hardware consists of: ? one-time programmable (otp) non-volatile memories to store the aes key. two instances (otp1/2) are offered to store two keys. a 3rd otp (otp3) is used by the lpc18xx for storing other data. ? an aes engine to perform the aes decoding . this engine supports an external gpdma module to read and write data. the engine uses a 128-bit key and processes blocks of 128-bit. the key can use a dedicated hardware interface that is not visible to software or a so ftware interface. UM10430 chapter 4: lpc18xx security features rev. 00.13 ? 20 july 2011 user manual www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 34 of 1164 nxp semiconductors UM10430 chapter 4: lpc18xx security features 4.4 aes api calls 4.4.1 security api the security api controls the aes block. fig 16. aes engine aes engine otp controller otp2 vpp 3v3 vdd 1v2 aes_key ahb otp1 otp0 rng cpu jtag gpdma control data ahb2 apb table 11. security api calls function offset relative to the api entry point description aes_api_set_mode 0x00 defines ae s engine o peration mode parameter: unsigned cmd with values: 0 - reserved. do not use. 1 - aes_api_cmd_decode_ecb 2 - reserved. do not use. 3 - aes_api_cmd_decode_cbc return - unsigned: see general error codes. aes_api_load_key_1 0x04 loads 128 bit aes user key 1 parameter - void return - void aes_api_load_key_2 0x08 loads 128 bit aes user key 2 parameter - void return - void aes_api_load_key_rng 0x0c loads randomly generated key in aes engine. parameter - void return - void www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 35 of 1164 nxp semiconductors UM10430 chapter 4: lpc18xx security features 4.4.2 otp memory the virgin otp state is all zeros. this implies that a zero value can be overwritten by a one value, but a one value cannot be changed. programming the otp requires a higher voltage than reading. the read voltage is generated internally. the programming voltage is supplied via pin vpp. if this pin is not connected, then the otp can not be programmed. the otp controller automatically selects the correct voltage. aes_api_load_key_sw 0x10 loads 128 bit aes software defined user key parameter - unsigned char *key(16 bytes) return - void aes_api_load_iv_sw 0x14 loads 128 bit aes init vector parameter - unsigned char *iv(16 bytes) return - void aes_api_load_iv_ic 0x18 loads 128 bit aes ic specific init vector, which is used to decode a boot image. parameter - void return - void aes_api_operate 0x1c performs an operation pre-selected by the selected mode and therefore a key. a previously loaded iv is used. data_out=aes_op(data_i n*size, key, [iv]) parameter 1 - unsigned char *data_out parameter 2 - unsigned char *data_in parameter 3 - unsigned size (128 bits word - 16 bytes) return - unsigned: see general error codes. aes_api_program_key_1 0x20 programs 128 bit aes key in otp. parameter: unsigned char *key (16 bytes) return - unsigned: see general error codes. aes_api_program_key_2 0x24 programs 128 bit aes key in otp. parameter: unsigned char *key (16 bytes) return - unsigned: see general error codes. table 11. security api calls function offset relative to the api entry point description www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 36 of 1164 5.1 how to read this chapter remark: this chapter describes th e nvic connections of pa rts lpc1850/30/20/10 rev ?a?. the available nvic interrupt sources vary for different parts. ? ethernet interrupt: available on lpc1850/30. ? usb0 interrupt: available on lpc1850/30/20. ? usb1 interrupt: available on lpc1850/30. 5.2 basic configuration the nvic is part of the arm cortex-m3 core. 5.3 features ? nested vectored interrupt controller that is an integral part of the arm cortex-m3 ? tightly coupled interrupt controller provides low interrupt latency ? controls system exceptions and peripheral interrupts ? on the lpc18xx, the nvic supports 32 vectored interrupts ? 32 programmable interrupt priority levels , with hardware pr iority level masking ? relocatable vector table ? non-maskable interrupt ? software interr upt generation 5.4 general description the nested vectored in terrupt controller (nvic) is an integral part of the cortex-m3. the tight coupling to the cpu allows for low interr upt latency and efficient processing of late arriving interrupts. refer to the cortex-m3 user gui de for details of nvic operation. 5.5 pin description UM10430 chapter 5: lpc18xx nvic rev. 00.13 ? 20 july 2011 user manual table 12. nvic pin description function direction description nmi i external non-maskable interrupt (nmi) input www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 37 of 1164 nxp semiconductors UM10430 chapter 5: lpc18xx nvic 5.6 interrupt sources ta b l e 1 3 lists the interrupt sources for each peripheral function. each peripheral device may have one or more interrupt lines to the vectored interrupt controller. each line may represent more than one interrupt source, as noted. exception numbers relate to where entries ar e stored in the exception vector table. interrupt numbers are used in some other contexts, such as software interrupts. in addition, the nvic handles the non-maskab le interrupt (nmi). in order for nmi to operate from an external signal, the nmi func tion must be connected to the related device pin (p4_0 or pe_4). w hen connected, a logic one on t he pin will cause the nmi to be processed. for details, refer to the cortex-m3 user guide. table 13. connection of interrupt sources to the nvic interrupt id exception number vector offset function flag(s) 016 0x40dac 1 17 0x44 - reserved 218 0x48dma 3 19 0x4c - reserved 4 20 0x50 - reserved 5 21 0x54 ethernet ethernet interrupt sbd_intr_o 6 22 0x58 sd/mmc 723 0x5clcd 8 24 0x60 usb0 otg interrupt 9 25 0x64 usb1 otg interrupt 10 26 0x68 sct sct combined interrupt 11 27 0x6c ri timer 12 28 0x70 timer0 13 29 0x74 timer1 14 30 0x78 timer2 15 31 0x7c timer3 16 32 0x80 motor control pwm 17 33 0x84 adc0 18 34 0x88 i2c0 19 35 0x8c i2c1 20 36 0x90 - reserved 21 37 0x94 adc1 22 38 0x98 ssp0 23 39 0x9c ssp1 24 40 0xa0 usart0 25 41 0xa4 uart1 uart and modem interrupt 26 42 0xa8 usart2 27 43 0xac usart3 usart and irda interrupt 28 44 0xb0 i2s0 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 38 of 1164 nxp semiconductors UM10430 chapter 5: lpc18xx nvic 5.7 register description the following table summarizes the registers in the nvic as implemented in the lpc18xx. the cortex-m3 user guide provides a functional description of the nvic. 29 45 0xb4 i2s1 30 46 0xb8 spifi 31 47 0xbc - reserved 32 48 0xc0 gpio pin interrupt 0 33 49 0xc4 gpio pin interrupt 1 34 50 0xc8 gpio pin interrupt 2 35 51 0xcc gpio pin interrupt 3 36 52 0xd0 gpio pin interrupt 4 37 53 0xc4 gpio pin interrupt 5 38 54 0xc8 gpio pin interrupt 6 39 55 0xcc gpio pin interrupt 7 40 56 0xd0 gpio group interrupt 0 41 57 0xd4 gpio group interrupt 1 42 58 0xd8 event router combined interrupt from the event router sources 43 59 0xdc c_can1 interrupt 44 60 0xe0 reserved 45 61 0xe4 reserved 46 62 0xe8 atimer 47 63 0xec reserved 48 64 0xf0 reserved 49 65 0xf4 wwdt 50 66 0xf8 reserved 51 67 0xfc c_can0 52 68 0x100 qei table 13. connection of interrupt sources to the nvic interrupt id exception number vector offset function flag(s) table 14. register overview: nvic (base address 0xe000 e000) name access address offset description reset value iser0 rw 0x100 interrupt set-enable register 0. this register allows enabling interrupts and reading back the interrupt enables for specific peripheral functions. 0 iser1 rw 0x104 interrupt set-enable register 1. this register allows enabling interrupts and reading back the interrupt enables for specific peripheral functions. 0 icer0 rw 0x180 interrupt clear-enable register 0. this register allows disabling interrupts and reading back the interrupt enables for specific peripheral functions. 0 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 39 of 1164 nxp semiconductors UM10430 chapter 5: lpc18xx nvic icer1 rw 0x184 interrupt clear-enable register 1. this register allows disabling interrupts and reading back the interrupt enables for specific peripheral functions. 0 ispr0 rw 0x200 interrupt set-pending register 0. this register allows changing the interrupt state to pending and reading back the interrupt pending state for specific peripheral functions. 0 ispr1 rw 0x204 interrupt set-pending register 1. this register allows changing the interrupt state to pending and reading back the interrupt pending state for specific peripheral functions. 0 icpr0 rw 0x280 interrupt clear-pending register 0. this register allows changing the interrupt state to not pending and reading back the interrupt pending state for specific peripheral functions. 0 icpr1 rw 0x284 interrupt clear-pending register 0. this register allows changing the interrupt state to not pending and reading back the interrupt pending state for specific peripheral functions. 0 iabr0 ro 0x300 interrupt active bit register 0. th is register allows readi ng the current interrupt active state for specific peripheral functions. 0 iabr1 ro 0x304 interrupt active bit register 1. th is register allows readi ng the current interrupt active state for specific peripheral functions. 0 ipr0 rw 0x400 interrupt priority registers 0. this register allows assigning a priority to each interrupt. each register contains the 5-bit priority fields for 4 interrupts. 0 ipr1 rw 0x404 interrupt priority registers 1 this register allows assigning a priority to each interrupt. each register contains the 5-bit priority fields for 4 interrupts. 0 ipr2 rw 0x408 interrupt priority registers 2. this register allows assigning a priority to each interrupt. each register contains the 5-bit priority fields for 4 interrupts. 0 ipr3 rw 0x40c interrupt priority registers 3. this register allows assigning a priority to each interrupt. each register contains the 5-bit priority fields for 4 interrupts. 0 ipr4 rw 0x410 interrupt priority registers 4. this register allows assigning a priority to each interrupt. each register contains the 5-bit priority fields for 4 interrupts. 0 ipr5 rw 0x414 interrupt priority registers 5. this register allows assigning a priority to each interrupt. each register contains the 5-bit priority fields for 4 interrupts. 0 ipr6 rw 0x418 interrupt priority registers 6. this register allows assigning a priority to each interrupt. each register contains the 5-bit priority fields for 4 interrupts. 0 ipr7 rw 0x41c interrupt priority registers 7. this register allows assigning a priority to each interrupt. each register contains the 5-bit priority fields for 4 interrupts. 0 stir wo 0xf00 software trigger interrupt register. this register allows software to generate an interrupt. 0 table 14. register overview: nvic (base address 0xe000 e000) ?continued name access address offset description reset value www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 40 of 1164 6.1 how to read this chapter remark: this chapter applies to parts lpc1850/30/30/10 rev ?a? only. remark: the event router controls the wake-up pr ocess and various event inputs to the nvic. the available event router sources vary for different parts. ? ethernet: available on lpc1850/30. ? usb0: available on lpc1850/30/20. ? usb1: available on lpc1850/30. 6.2 basic configuration ? see ta b l e 1 5 for clocking. ? an event created in the event router can be output on the rtc_alarm pin (see ta b l e 3 1 ). ? the event router is connected to interrupt #42 in the nvic (see table 13 ). 6.3 general description the event router is used to process wake-up events such as certain interrupts and external or internal inputs for wake-up from any of the low power modes (sleep, deep-sleep, power-down, and deep power-down modes). the event router has multiple event inputs from various peripherals. when the proper edge detection is set in the edge configuration register, the event router can wake up the part or can raise an interrupt in the nvic. each event input to the event router can be co nfigured to trigger an output signal on rising or falling edges or on high or low levels. the event router combines all events to an output signal which is used as follows: ? create an interrupt if the event router interrupt is enabled in the nvic. ? send a wake-up signal to the power management unit to wake up from deep-sleep, power-down, and deep power-down modes. ? send a wake-up signal to ccu1 and ccu2 for waking up fr om sleep mode (see section 14.5.3 ). UM10430 chapter 6: lpc18xx event router rev. 00.13 ? 20 july 2011 user manual table 15. event router clocking and power control base clock branch clock maximum frequency clock to event router base_ m3_clk clk_m3_bus 150 mhz www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 41 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router 6.4 event router inputs 6.5 pin description table 16. event router inputs event # source notes 0 wakeup0 wakeup0 pin 1 wakeup1 wakeup1 pin 2 wakeup2 wakeup2 pin 3 wakeup3 wakeup3 pin 4 alarm timer alarm timer interrupt 5 rtc rtc interrupt 6 bod trip level 1 bod interrupt; wake-up from low power mode 7 wwdt wwdt interrupt 8 ethernet wake-up packet indicator 9 usb0 wake-up request signal 10 usb1 ahb_needclk signal 11 sd/mmc sd/mmc interrupt 12 c_can0/1 ored c_can0 and c_can1 interrupt 13 gima output 25 output 2 of the co mbined timer (ored output of sct output 2 and the match channel 2 of timer 0). see table 134 . 14 gima output 26 output 6 of the co mbined timer (ored output of sct output 6 and the match channel 2 of timer 1). see table 134 . 15 qei qei interrupt 16 gima output 27 output 14 of the combined timer (ored output of sct output 14 and the match channel 2 of timer 3). see table 134 . 17 - reserved 18 - reserved 19 reset 20 bod trip level 2 25-21 - reserved table 17. event router pin description pin direction description wakeup0/1/2/3 i external wake-up input ; can raise an interrupt and can cause wake-up from any of the low power modes. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 42 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router 6.6 register description 6.6.1 level configuration register this register works in combination with the edge configuration register edge (see ta b l e 2 1 ) to configure the level and edge detection for each input to the event router. table 18. register overview: event router (base address 0x4004 4000) name access address offset description reset value hilo r/w 0x000 level configuration register 0x000 edge r/w 0x004 edge configuration 0x000 - - 0x008 - 0xfd4 reserved - clr_en w 0xfd8 event clear enable register 0x0 set_en w 0xfdc event set enable register 0x0 status r 0xfe0 status register 0x0 enable r 0xfe4 enable register 0x0 clr_stat w 0xfe8 clear register 0x0 set_stat w 0xfec set register 0x0 table 19. level configuration register (h ilo - address 0x4004 4000) bit description bit symbol value description reset value 0 wakeup0_l level detect mode for wakeup0 event. 0 0 detect low level if bit 0 in th e edge register is 0. detect falling edge if bit 0 in the edge register is 1. 1 detect high level if bit 0 in th e edge register is 0. detect rising edge if bit 0 in the edge register is 1. 1 wakeup1_l level detect mode for wakeup1 event. the corresponding bit in the edge register must be 0. 0 0 detect low level if bit 1 in the edge register is 0. 1 detect high level if bit 1 in th e edge register is 0. detect rising edge if bit 1 in the edge register is 1. 2 wakeup2_l level detect mode for wakeup2 event. 0 0 detect low level if bit 2 in th e edge register is 0. detect falling edge if bit 2 in the edge register is 1. 1 detect high level if bit 2 in th e edge register is 0. detect rising edge if bit 2 in the edge register is 1. 3 wakeup3_l level detect mode for wakeup3 event. 0 0 detect low level if bit 3 in th e edge register is 0. detect falling edge if bit 3 in the edge register is 1. 1 detect high level if bit 3 in th e edge register is 0. detect rising edge if bit 3 in the edge register is 1. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 43 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router 4 atimer_l level detect mode for alarm timer event. 0 0 detect low level if bit 4 in th e edge register is 0. detect falling edge if bit 4 in the edge register is 1. 1 detect high level if bit 4 in th e edge register is 0. detect rising edge if bit 4 in the edge register is 1. 5 rtc_l level detect mode for rtc event. 0 0 detect low level if bit 5 in th e edge register is 0. detect falling edge if bit 5 in the edge register is 1. 1 detect high level if bit 5 in th e edge register is 0. detect rising edge if bit 5 in the edge register is 1. 6 bod_l level detect mode for bod event. 0 0 detect low level if bit 6 in th e edge register is 0. detect falling edge if bit 6 in the edge register is 1. 1 detect high level if bit 6 in th e edge register is 0. detect rising edge if bit 6 in the edge register is 1. 7 wwdt_l level detect mode for wwdtd event. 0 0 detect low level if bit 7 in th e edge register is 0. detect falling edge if bit 7 in the edge register is 1. 1 detect high level if bit 7 in th e edge register is 0. detect rising edge if bit 7 in the edge register is 1. 8eth_l 0 0 detect low level if bit 8 in th e edge register is 0. detect falling edge if bit 8 in the edge register is 1. 1 detect high level if bit 8 in th e edge register is 0. detect rising edge if bit 8 in the edge register is 1. 9 usb0_l 0 0 detect low level if bit 9 in th e edge register is 0. detect falling edge if bit 9 in the edge register is 1. 1 detect high level if bit 9 in th e edge register is 0. detect rising edge if bit 9 in the edge register is 1. 10 usb1_l 0 0 detect low level if bit 10 in th e edge register is 0. detect falling edge if bit 10 in the edge register is 1. 1 detect high level if bit 10 in the edge register is 0. detect rising edge if bit 10 in the edge register is 1. 11 - - reserved. 12 can_l level detect mode for c_can event. 0 0 detect low level if bit 12 in th e edge register is 0. detect falling edge if bit 12 in the edge register is 1. 1 detect high level if bit 12 in the edge register is 0. detect rising edge if bit 12 in the edge register is 1. table 19. level configuration register (h ilo - address 0x4004 4000) bit description bit symbol value description reset value www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 44 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router 6.6.2 edge configuration register this register works in combination with th e level configuration register hilo (see ta b l e 1 9 ) to configure the level or edge detection for each input to the event router. the edge configuration register determines whether the event router responds to a level change (edgen=1), or a constant level (edgen=0). the hilon bit determines a response to a rising edge (hilon=1) or a falling edge (hilon=0). 13 tim2_l level detect mode for combined timer output 2 event. 0 0 detect low level if bit 13 in th e edge register is 0. detect falling edge if bit 13 in the edge register is 1. 1 detect high level if bit 13 in the edge register is 0. detect rising edge if bit 13 in the edge register is 1. 14 tim6_l level detect mode for combined timer output 6 event. 0 0 detect low level if bit 14 in th e edge register is 0. detect falling edge if bit 14 in the edge register is 1. 1 detect high level if bit 14 in the edge register is 0. detect rising edge if bit 14 in the edge register is 1. 15 qei_l level detect mode for qei event. 0 0 detect low level if bit 15 in th e edge register is 0. detect falling edge if bit 15 in the edge register is 1. 1 detect high level if bit 15 in the edge register is 0. detect rising edge if bit 15 in the edge register is 1. 16 tim14_l level detect mode for combined timer output 14 event. 0 0 detect low level if bit 16 in th e edge register is 0. detect falling edge if bit 16 in the edge register is 1. 1 detect high level if bit 16 in the edge register is 0. detect rising edge if bit 16 in the edge register is 1. 18:17 - - reserved. 19 reset_l . 0 0 detect low level if bit 17 in th e edge register is 0. detect falling edge if bit 17 in the edge register is 1. 1 detect high level if bit 17 in the edge register is 0. detect rising edge if bit 17 in the edge register is 1. 31:20 - - reserved. table 19. level configuration register (h ilo - address 0x4004 4000) bit description bit symbol value description reset value table 20. edge and hilo combined register settings hilon edgen description 0 0 detect low level 0 1 detect falling edge 1 0 detect high level 1 1 detect rising edge www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 45 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router when a high level detect is active, the event router status bits cannot be cleared until the signal is low. when a rising edge detect is active, the event router status bit can be cleared right after the event has occurred. table 21. edge configuration register (edge - address 0x4004 4004) bit description bit symbol value description reset value 0 wakeup0_e edge detect mode for wakeup0 event. 0 0 level detect. 1 edge detect. detect falling edge if bit 0 in the hilo register is 0. detect rising edge if bit 0 in the hilo register is 1. 1 wakeup1_e edge/level detect m ode for wakeup1 event. the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 1 in the hilo register is 0. detect rising edge if bit 1 in the hilo register is 1. 2 wakeup2_e edge/level detect m ode for wakeup2 event. the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 2 in the hilo register is 0. detect rising edge if bit 2 in the hilo register is 1. 3 wakeup3_e edge/level detect m ode for wakeup3 event. the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 30 in the hilo register is 0. detect rising edge if bit 3 in the hilo register is 1. 4 atimer_e edge/level detect mode for alarm timer event. the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 4 in the hilo register is 0. detect rising edge if bit 4 in the hilo register is 1. 5 rtc_e edge/level detect mode for rtc event. the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 5 in the hilo register is 0. detect rising edge if bit 5 in the hilo register is 1. 6 bod_e edge/level detect mode for bod event. the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 6 in the hilo register is 0. detect rising edge if bit 6 in the hilo register is 1. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 46 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router 7 wwdt_e edge/level detect mode for wwdtd event. the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 7 in the hilo register is 0. detect rising edge if bit 7 in the hilo register is 1. 8 eth_e the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 8 in the hilo register is 0. detect rising edge if bit 8 in the hilo register is 1. 9 usb0_e the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 9 in the hilo register is 0. detect rising edge if bit 9 in the hilo register is 1. 10 usb1_e the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 10 in the hilo register is 0. detect rising edge if bit 10 in the hilo register is 1. 11 - - reserved. 12 can_e edge/level detect mode for c_can event. the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 12 in the hilo register is 0. detect rising edge if bit 12 in the hilo register is 1. 13 tim2_e edge/level detect mode for combined timer output 2 event. the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 13 in the hilo register is 0. detect rising edge if bit 13 in the hilo register is 1. 14 tim6_e edge/level detect mode for combined timer output 6 event. the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 14 in the hilo register is 0. detect rising edge if bit 14 in the hilo register is 1. table 21. edge configuration register (edge - address 0x4004 4004) bit description bit symbol value description reset value www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 47 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router 6.6.3 interrupt clear enable register 15 qei_e edge/level detect mode for qei interrupt signal. the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 15 in the hilo register is 0. detect rising edge if bit 15 in the hilo register is 1. 16 tim14_e edge/level detect mode for combined timer output 14 event. the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 16 in the hilo register is 0. detect rising edge if bit 16 in the hilo register is 1. 18:17 - - reserved. 19 reset_e . the corresponding bit in the edge register must be 0. 0 0 level detect. 1 edge detect. detect falling edge if bit 19 in the hilo register is 0. detect rising edge if bit 19 in the hilo register is 1. 31:20 - - reserved. table 21. edge configuration register (edge - address 0x4004 4004) bit description bit symbol value description reset value table 22. interrupt clear enable register (c lr_en - address 0x4004 4fd8) bit description bit symbol description reset value 0 wakeup0_clren writing a 1 to this bit clears the event en able bit 0 in the enable register. - 1 wakeup1_clren writing a 1 to this bit clears the event en able bit 1 in the enable register. - 2 wakeup2_clren writing a 1 to this bit clears the event en able bit 2 in the enable register. - 3 wakeup3_clren writing a 1 to this bit clears the event en able bit 3 in the enable register. - 4 atimer_clren writing a 1 to this bit clears the event enable bit 4 in the enable register. - 5 rtc_clren writing a 1 to this bit clears the event enable bit 5 in the enable register. - 6 bod_clren writing a 1 to this bit clears the event enable bit 6 in the enable register. - 7 wwdt_clren writing a 1 to this bit clears the event enable bit 7 in the enable register. - 8 eth_clren writing a 1 to this bit clears the event enable bit 8 in the enable register. - 9 usb0_clren writing a 1 to this bit clears the event enable bit 9 in the enable register. - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 48 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router 6.6.4 event set enable register 10 usb1_clren writing a 1 to this bit clears the event enable bit 10 in the enable register. - 11 - reserved. - 12 can_clren writing a 1 to this bit clears the event enable bit 12 in the enable register. - 13 tim2_clren writing a 1 to this bit clears the event enable bit 13 in the enable register. - 14 tim6_clren writing a 1 to this bit clears the event enable bit 14 in the enable register. - 15 qei_clren writing a 1 to this bit clears the event enable bit 15 in the enable register. - 16 tim14_clren writing a 1 to this bit clears the event enable bit 16 in the enable register. - 18:17 - reserved. - 19 reset_clren writing a 1 to this bit cl ears the event enabl e bit 19 in the enable register. - 31:20 - reserved. - table 22. interrupt clear enable register (c lr_en - address 0x4004 4fd8) bit description bit symbol description reset value table 23. event set enable register (set_en - address 0x4004 4fdc) bit description bit symbol description reset value 0 wakeup0_seten writing a 1 to this bit sets the ev ent enable bit 0 in the enable register. - 1 wakeup1_seten writing a 1 to this bit sets the ev ent enable bit 1 in the enable register. - 2 wakeup2_seten writing a 1 to this bit sets the ev ent enable bit 2 in the enable register. - 3 wakeup3_seten writing a 1 to this bit sets the ev ent enable bit 3 in the enable register. - 4 atimer_seten writing a 1 to this bit sets the event enable bit 4 in the enable register. - 5 rtc_seten writing a 1 to this bit sets the event enable bit 5 in the enable register. - 6 bod_seten writing a 1 to this bit sets the event enable bit 6 in the enable register. - 7 wwdt_seten writing a 1 to this bit sets the event enable bit 7 in the enable register. - 8 eth_seten writing a 1 to this bit sets the event enable bit 8 in the enable register. - 9 usb0_seten writing a 1 to this bit sets the event enable bit 9 in the enable register. - 10 usb1_seten writing a 1 to this bit sets the event enable bit 10 in the enable register. - 11 - reserved. - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 49 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router 6.6.5 event status register 12 can_seten writing a 1 to this bit sets the event enable bit 12 in the enable register. - 13 tim2_seten writing a 1 to this bit sets the event enable bit 13 in the enable register. - 14 tim6_seten writing a 1 to this bit sets the event enable bit 14 in the enable register. - 15 qei_seten writing a 1 to this bit sets the event enable bit 15 in the enable register. - 16 tim14_seten writing a 1 to this bit sets the event enable bit 16 in the enable register. - 18:17 - reserved. - 19 reset_seten writing a 1 to this bit sets the event enable bit 19 in the enable register. - 31:20 - reserved. - table 23. event set enable register (set_en - address 0x4004 4fdc) bit description bit symbol description reset value table 24. interrupt status register (status - address 0x4004 4fe0) bit description bit symbol description reset value 0 wakeup0_st a 1 in this bit shows that the wakeup0 event has been raised. - 1 wakeup1_st a 1 in this bit shows that the wakeup1 event has been raised. - 2 wakeup2_st a 1 in this bit shows that the wakeup2 event has been raised. - 3 wakeup3_st a 1 in this bit shows that the wakeup3 event has been raised. - 4 atimer_st a 1 in this bit shows that the atimer event has been raised. - 5 rtc_st a 1 in this bit shows that the rtc event has been raised. - 6 bod_st a 1 in this bit shows that the bod event has been raised. - 7 wwdt_st a 1 in this bit shows that the wwdt event has been raised. - 8 eth_st a 1 in this bit shows that the ethernet event has been raised. - 9 usb0_st a 1 in this bit shows that the usb0 event has been raised. - 10 usb1_st a 1 in this bit shows that the usb1 event has been raised. - 11 - reserved. - 12 can_st a 1 in this bit shows that the c_can event has been raised. - 13 tim2_st a 1 in this bit shows that the combined timer 2 output event has been raised. - 14 tim6_st a 1 in this bit shows that the combined timer 6 output event has been raised. - 15 qei_st a 1 in this bit shows that the qei event has been raised. - 16 tim14_st a 1 in this bit shows that t he combined timer 14 output event has been raised. - 18:17 - reserved. - 19 reset_st a 1 in this bit shows that the event has been raised. - 31:20 - reserved. - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 50 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router 6.6.6 event enable register table 25. event enable register (enable - address 0x4004 4fe4) bit description bit symbol description reset value 0 wakeup0_en a 1 in this bit shows that the wakeup0 event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 1 wakeup1_en a 1 in this bit shows that the wakeup1 event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 2 wakeup2_en a 1 in this bit shows that the wakeup2 event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 3 wakeup3_en a 1 in this bit shows that the wakeup3 event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 4 atimer_en a 1 in this bit shows that the atimer event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 5 rtc_en a 1 in this bit shows that the rtc event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 6 bod_en a 1 in this bit shows that the bod event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 7 wwdt_en a 1 in this bit shows that the wwdt event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 8 eth_en a 1 in this bit shows that the ethernet event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 9 usb0_en a 1 in this bit shows that the usb0 event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 10 usb1_en a 1 in this bit shows that the usb1 event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 11 - reserved. - 12 can_en a 1 in this bit shows that the can event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 13 tim2_en a 1 in this bit shows that the tim2 event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 14 tim6_en a 1 in this bit shows that the tim6 event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 15 qei_en a 1 in this bit shows that the qei event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 51 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router 6.6.7 clear status register 16 tim14_en a 1 in this bit shows that the tim14 event has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 18:17 - - 19 reset_en a 1 in this bit shows th at the reset even t has been enabled. this event wakes up the chip and contributes to the event router interrupt when bit 0 = 1 in the status register. 0 31:20 - reserved. - table 25. event enable register (enable - address 0x4004 4fe4) bit description bit symbol description reset value table 26. interrupt clear status register (c lr_stat - address 0x4004 4fe8) bit description bit symbol description reset value 0 wakeup0_clrst writing a 1 to this bi t clears the status event bit 0 in the status register. 1 wakeup1_clrst writing a 1 to this bi t clears the status event bit 1 in the status register. 2 wakeup2_clrst writing a 1 to this bi t clears the status event bit 2 in the status register. 3 wakeup3_clrst writing a 1 to this bi t clears the status event bit 3 in the status register. 4 atimer_clrst writing a 1 to this bit clears the status event bit 4 in the status register. 5 rtc_clrst writing a 1 to this bit clears the status event bit 5 in the status register. 6 bod_clrst writing a 1 to this bit clears the status event bit 6 in the status register. 7 wwdt_clrst writing a 1 to this bit clears the status event bit 7 in the status register. 8 eth_clrst writing a 1 to this bit clears the status event bit 8 in the status register. 9 usb0_clrst writing a 1 to this bit clears the status event bit 9 in the status register. 10 usb1_clrst writing a 1 to this bit clears the status event bit 10 in the status register. 11 - reserved. 12 can_clrst writing a 1 to this bit clears the status event bit 12 in the status register. 13 tim2_clrst writing a 1 to this bit clears the status event bit 13 in the status register. 14 tim6_clrst writing a 1 to this bit clears the status event bit 14 in the status register. 15 qei_clrst writing a 1 to this bit clears the status event bit 15 in the status register. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 52 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router 6.6.8 set status register 16 tim14_clrst writing a 1 to this bit clears the status event bit 16 in the status register. 18:17 - 19 reset_clrst writing a 1 to this bit clears the status event bit 19 in the status register. 31:20 - reserved. - table 26. interrupt clear status register (c lr_stat - address 0x4004 4fe8) bit description bit symbol description reset value table 27. interrupt set status register (set _stat - address 0x4004 4fec) bit description bit symbol description reset value 0 wakeup0_setst writing a 1 to this bit sets the status event bit 0 in the status register. 1 wakeup1_setst writing a 1 to this bit sets the status event bit 1 in the status register. 2 wakeup2_setst writing a 1 to this bit sets the status event bit 2 in the status register. 3 wakeup3_setst writing a 1 to this bit sets the status event bit 3 in the status register. 4 atimer_setst writing a 1 to this bit sets the status event bit 4 in the status register. 5 rtc_setst writing a 1 to this bit sets the status event bit 5 in the status register. 6 bod_setst writing a 1 to this bit sets the status event bit 6 in the status register. 7 wwdt_setst writing a 1 to this bit sets the status event bit 7 in the status register. 8 eth_setst writing a 1 to this bit sets the status event bit 8 in the status register. 9 usb0_setst writing a 1 to this bit sets the status event bit 9 in the status register. 10 usb1_setst writing a 1 to this bit sets the status event bit 10 in the status register. 11 - reserved. 12 can_setst writing a 1 to this bit sets the status event bit 12 in the status register. 13 tim2_setst writing a 1 to this bit sets the status event bit 13 in the status register. 14 tim6_setst writing a 1 to this bit sets the status event bit 14 in the status register. 15 qei_setst writing a 1 to this bit sets the status event bit 15 in the status register. 16 tim14_setst writing a 1 to this bit sets the status event bit 16 in the status register. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 53 of 1164 nxp semiconductors UM10430 chapter 6: lpc18xx event router 18:17 - reserved. 19 reset_setst writing a 1 to this bit sets the status ev ent bit 19 in the status register. 31:20 - reserved. - table 27. interrupt set status register (set _stat - address 0x4004 4fec) bit description bit symbol description reset value www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 54 of 1164 7.1 how to read this chapter remark: this chapter applies to lpc1 850/30/20/10 rev ?a? only. the available peripherals vary for different parts. ? ethernet: available on lpc1850/30. ? usb0: available on lpc1850/30/20. ? usb1: available on lpc1850/30. if a peripheral is not available, the corresponding bits in the creg registers are reserved. 7.2 basic configuration the creg block is configured as follows: ? see ta b l e 2 8 for clocking and power control. ? the creg block can not be reset by software. 7.3 features the following settings are controlled in the configuration register block: ? bod trip settings ? oscillator output ? dma-to-peripheral muxing ? ethernet mode ? memory mapping ? timer/uart inputs ? in addition, the creg block contains the part id and the part configuration information. UM10430 chapter 7: lpc18xx configuration registers (creg) rev. 00.13 ? 20 july 2011 user manual table 28. creg clocking and power control base clock branch clock maximum frequency creg base_m3_clk clk_m3_creg 150 mhz www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 55 of 1164 nxp semiconductors UM10430 chapter 7: lpc18xx confi guration registers (creg) 7.4 register description 7.4.1 irc trim register table 29. register overview: configuration registers (base address 0x4004 3000) name access address offset description reset value irctrm ro 0x000 irc trim register 0x000f f2bc creg0 r/w 0x004 chip configuration regist er 32 khz oscillator output and bod control register. pmucon 0x008 power mode cont rol register. 0x0000 0000 - - 0x008 - 0x0fc reserved - m3memmap r/w 0x100 arm cortex-m3 memory mapping - - 0x104 reserved - creg1 ro 0x108 chip configuration register 1 creg2 ro 0x10c chip configuration register 2 creg3 ro 0x110 chip configuration register 3 creg4 ro 0x114 chip configuration register 4 creg5 r/w 0x118 chip configuration regi ster 5. controls jtag access. dmamux r/w 0x11c dma muxing control - - 0x120 - 0x124 reserved - etbcfg r/w 0x128 etb ram configuration 0x0000 0000 creg6 r/w 0x12c - - 0x130 - 0x1fc reserved - chipid ro 0x200 part id - - 0x204 - 0x2fc reserved - - - 0x300 0x304 0x308 - - 0x30c - 0xefc reserved - lockreg 0xf00 lock register; blo cks write access to creg registers table 30. irc trim register (irctrm, address 0x4004 3000) bit description bit symbol description reset value access 11:0 trm irc trim value 0x2bc r 19:12 - reserved 0xff r 31:20 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 56 of 1164 nxp semiconductors UM10430 chapter 7: lpc18xx confi guration registers (creg) 7.4.2 creg0 control register 7.4.3 power mode control register for details on power mode selection, see section 8.2 . table 31. creg0 register (creg0, address 0x4004 3004) bit description bit symbol value description reset value access 0 en1khz enable 1 khz output. 0 r/w 0 1 khz output disabled. 1 1 khz output enabled. 1 en32khz enable 32 khz output 0 r/w 0 32 khz output disabled. 1 32 khz output enabled. 2 reset32khz 32 khz oscillator reset 1 r/w 0 1 3 32khzpd 32 khz power control. 1 r/w 0 32 khz oscillator powered. 1 32 khz oscillator powered-down. 4- reserved - - 5 usb0phy usb0 phy powe r control. r/w 0 usb0 phy powered. 1 usb0 phy powered down. 7:6 alarmctrl rtc_alarm pi n output control r/w 0x0 rtc alarm. 0x1 event router event. 0x2 event router or . 0x3 inactive. 9:8 bodlvl1 bod trip level to generate an interrupt. 11 r/w 0x0 2.75 v 0x1 2.85 v 0x2 2.95 v 0x3 3.05 v 11:10 bodlvl2 bod trip level to generate a reset. 11 r/w 0x0 1.70 v 0x1 1.80 v 0x2 1.90 v 0x3 2.00 v 31:12 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 57 of 1164 nxp semiconductors UM10430 chapter 7: lpc18xx confi guration registers (creg) 7.4.4 arm cortex-m3 me mory mapping register 7.4.5 creg5 control register 7.4.6 dma muxing register this register controls which set of peripher als is connected to the dma controller (see table 195 ). table 32. power mode control register (pmu con, address 0x4004 3008) bit description bit symbol value description reset value access 1:0 pmucon controls power mode. 0 r/w 0x0 normal 0x1 low-power 0x2 reserved 0x3 normal 31:2 - reserved - - table 33. memory mapping register (m3memmap, address 0x4004 3100) bit description bit symbol description reset value access 11:0 reserved 0x000 - 31:12 m3map shadow address when accessing memory at address 0x0000 0000 0x1040 0000 r/w table 34. creg5 control register (creg5, address 0x4004 3118) bit description bit symbol description reset value access 4:0 - reserved. - - 5 - reserved. 0 - 6 m3tapsel 0 r/w 7 - reserved. 0 - 8 - reserved. 0 - 31:9 - reserved. - - table 35. dma muxing register (dmamux, address 0x4004 311c) bit description bit symbol value description reset value access 1:0 dmamuxch0 select dma to peripheral connection for dma peripheral 0. 0r/w 0x0 spifi 0x1 sct match 2 0x2 reserved 0x3 t3 match 1 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 58 of 1164 nxp semiconductors UM10430 chapter 7: lpc18xx confi guration registers (creg) 3:2 dmamuxch1 select dma to peripheral connection for dma peripheral 1 0r/w 0x0 timer 0 match 0 0x1 usart0 transmit 0x2 reserved 0x3 aes input 5:4 dmamuxch2 select dma to peripheral connection for dma peripheral 2. 0r/w 0x0 timer 0 match 1 0x1 usart0 receive 0x2 reserved 0x3 aes output 7:6 dmamuxch3 select dma to peripheral connection for dma peripheral 3. 0r/w 0x0 timer 1 match 0 0x1 uart1 transmit 0x2 i2s1 channel 0 0x3 ssp1 transmit 9:8 dmamuxch4 select dma to peripheral connection for dma peripheral 4. 0r/w 0x0 timer 1 match 1 0x1 uart1 receive 0x2 i2s1 channel 1 0x3 ssp1 receive 11:10 dmamuxch5 select dma to peripheral connection for dma peripheral 5. 0r/w 0x0 timer 2 match 0 0x1 usart2 transmit 0x2 ssp1 transmit 0x3 reserved 13:12 dmamuxch6 selects dma to peripheral connection for dma peripheral 6. 0r/w 0x0 timer 2 match 1 0x1 usart2 receive 0x2 ssp1 receive 0x3 reserved 15:14 dmamuxch7 selects dma to peripheral connection for dma peripheral 7. 0r/w 0x0 timer 3 match l 0 0x1 usart3 transmit 0x2 sct match output 0 0x3 reserved table 35. dma muxing register (dmamux, address 0x4004 311c) bit description ?continued bit symbol value description reset value access www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 59 of 1164 nxp semiconductors UM10430 chapter 7: lpc18xx confi guration registers (creg) 17:16 dmamuxch8 select dma to peripheral connection for dma peripheral 8. 0r/w 0x0 timer 3 match 1 0x1 usart3 receive 0x2 sct match output 1 0x3 reserved 19:18 dmamuxch9 select dma to peripheral connection for dma peripheral 9. 0r/w 0x0 ssp0 receive 0x1 i2s0 channel 0 0x2 sct match output 1 0x3 reserved 21:20 dmamuxch10 select dma to peripheral connection for dma peripheral 10. 0r/w 0x0 ssp0 transmit 0x1 i2s0 channel 1 0x2 sct match output 0 0x3 reserved 23:22 dmamuxch11 selects dma to peripheral connection for dma peripheral 11. 0r/w 0x0 ssp1 receive 0x1 reserved 0x2 usart0 transmit 0x3 reserved 25:24 dmamuxch12 select dma to peripheral connection for dma peripheral 12. 0r/w 0x0 ssp1 transmit 0x1 reserved 0x2 usart0 receive 0x3 reserved 27:26 dmamuxch13 select dma to peripheral connection for dma peripheral 13. 0r/w 0x0 adc0 0x1 aes input 0x2 ssp1 receive 0x3 usart3 receive 29:28 dmamuxch14 select dma to peripheral connection for dma peripheral 14. 0r/w 0x0 adc1 0x1 aes output 0x2 ssp1 transmit 0x3 usart3 transmit table 35. dma muxing register (dmamux, address 0x4004 311c) bit description ?continued bit symbol value description reset value access www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 60 of 1164 nxp semiconductors UM10430 chapter 7: lpc18xx confi guration registers (creg) 7.4.7 etb sram conf iguration register this register selects the interface that is used to the 16 kb block of ram located at address 0x2000 c000. this ram memory block can be accessed either by the etb or be used as normal sram on the ahb bus. note that by default, this memory area will be accessed by the etb. 7.4.8 creg6 control register this register controls various aspects of the lpc18xx: ? bits 2:0 control the ethernet phy interface. the ethernet block reads this register during set-up, and therefore the ethernet must be reset after changing the phy interface. ? bits 12:15 control the i2s connections. ? bit 16 controls the external memory controller clocking. 31:30 dmamuxch15 select dma to peripheral connection for dma peripheral 15. 0r/w 0x0 dac 0x1 sct match output 3 0x2 reserved 0x3 timer 3 match 0 table 35. dma muxing register (dmamux, address 0x4004 311c) bit description ?continued bit symbol value description reset value access table 36. etb sram configuration register (e tbcfg, address 0x4004 3128) bit description bit symbol value description reset value access 0 etb select sram interface 0 r/w 0 etb accesses sram at address 0x2000 c000. 1 ahb accesses sram at address 0x2000 c000. 31:1 - reserved. - - table 37. creg6 control register (creg6, address 0x4004 312c) bit description bit symbol value description reset value access 2:0 ethmode selects the ethernet mode. reset the ethernet after changing the phy interface. all other settings are reserved. r/w 0x0 mii 0x4 rmii 3 - reserved. r/w 4 timctrl 0 r/w 0 1 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 61 of 1164 nxp semiconductors UM10430 chapter 7: lpc18xx confi guration registers (creg) 7.4.9 part id register 11: 5 - reserved. - - 12 i2s0_tx_sck_in_ sel i2s0_tx_sck input select 0 r/w 0 i2 s clock selected as defined by the i2s transmit mode register table 744 . 1 audio pll for i2s transmit clock mclk input and mclk output. the i2s must be configured in slave mode. 13 i2s0_rx_sck_in_ sel i2s0_rx_sck input select 0 r/w 0 i2 s clock selected as defined by the i2s receive mode register table 745 . 1 audio pll for i2s receive clock mclk input and mclk output. the i2s must be configured in slave mode. 14 i2s1_tx_sck_in_ sel i2s1_tx_sck input select 0 r/w 0 i2 s clock selected as defined by the i2s transmit mode register table 744 . 1 audio pll for i2s transmit clock mclk input and mclk output. the i2s must be configured in slave mode. 15 i2s1_rx_sck_in_ sel i2s1_rx_sck input select 0 r/w 0 i2 s clock selected as defined by the i2s receive mode register table 745 . 1 audio pll for i2s receive clock mclk input and mclk output. the i2s must be configured in slave mode. 16 emc_clk_sel emc_clk divi ded clock select (see section 19.1 ). 0r/w 0 emc_clk_div not divided. 1 emc_clk_div divided by 2. 31: 17 - reserved. - - table 37. creg6 control register (creg6, address 0x4004 312c) bit description ?continued bit symbol value description reset value access table 38. part id register (chipid, address 0x4004 3200) bit description bit symbol description reset value access 31:0 id www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 62 of 1164 8.1 how to read this chapter the power management controller is identical on all lpc18xx parts. 8.2 general description the pmc implements the control sequences to enable transitioning between different power modes and controls the power state of ea ch peripheral. in addition, wake-up from a low-power mode based on hardware events is supported. low-power modes can be reached from active mode only, and transitions between low-power modes are not allowed. the pmc supports the following low-power modes: deep-sleep, power-down, and deep power-down. the wake-up from a low-power mode will always result in the active mode. the lpc18xx supports five power modes in order from highest to lowest power consumption: 1. active mode 2. sleep mode (controlled by the arm cortex-m3 core) 3. deep-sleep mode (controlled by the arm cortex-m3 core) 4. power-down mode (controlled by the arm cortex-m3 core) 5. deep power-down mode 8.2.1 active mode by default, the lpc18xx is in active m ode, which means that every peripheral can perform a functional operation at nominal operating conditions. the other low-power modes are standby modes in which the peripheral clocks are disabled and operating conditions are adapted to achieve further power savings. the peripheral clocks are enabled again at wake-up. in active (or sleep mode), three operating modes are supported. ? low-power mode: the cpu and core logic operate slower and the core supply voltage is reduced. ? normal mode: the cpu operates at the nominal supply voltage. the operating modes are programmable through a power api and through the pmucon register in the creg block (see ta b l e 3 2 ). 8.2.2 sleep mode in sleep mode the cpu clock is shut down to save power; the periph erals can still remain active and fully functional. the sleep mode is entered by a wfi or wfe instruction if the sleepdeep bit in the arm cortex-m3 syst em control register is set to 0. UM10430 chapter 8: lpc18xx power ma nagement controller (pmc) rev. 00.13 ? 20 july 2011 user manual www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 63 of 1164 nxp semiconductors UM10430 chapter 8: lpc18xx power management controller (pmc) as in active mode, low-power and normal modes can be selected. 8.2.3 deep-sleep mode in deep-sleep mode the cpu clock and peripheral clocks are shut down to save power; logic states and sram memory are maintained. all analog blocks and the bod control circuit are powered down. the deep-sleep mode is entered by a wfi or wfe instruction if the sleepdeep bit in the arm cortex-m3 syste m control register is set to 1 and the pd0_sleep0_mode register (see ta b l e 4 1 ) is programmed with the deep-sleep mode value. when the lpc18xx wakes up from deep-sleep mode, the 12 mhz irc is used as the clock source for all base clocks. remark: before entering deep-sleep mode, program the cgu as follows: ? switch the clock source of all base clocks to the irc. ? put the plls in power-down mode. reprogramming the cgu avoids any undefined or unlocked pll clocks at wake-up and minimizes power consumption during deep-sleep mode. 8.2.4 power-down mode in power-down mode the cpu clock and peripheral clocks are shut down but logic states are maintained. all sram memory except for the upper 8 kb of the local sram located at 0x1008 0000, all analog blocks, and the bod control circuit are powered down.the power-down mode is ent ered by a wfi or wfe instruct ion if the sleepdeep bit in the arm cortex-m3 system control register is set to 1 and the pd0_sleep0_mode register (see table 41 ) is programmed with the power-down mode value. when the lpc18xx wakes up from power-down mode, the 12 mhz irc is used as the clock source for all base clocks. remark: before entering power-down mode, program the cgu as follows: ? switch the clock source of all base clocks to the irc. ? put the plls in power-down mode. reprogramming the cgu avoids any undefined or unlocked pll clocks at wake-up and minimizes power consumption during power-down mode. 8.2.5 deep power-down in deep power-down mode the entire core logic is powered down. only the logic in the rtc power domain remains active. the deep power-down mode is entered by a wfi or wfe instruction if the sleepdeep bit in the ar m cortex-m3 system co ntrol register is set to 1 and the pd0_sl eep0_mode register (see ta b l e 4 1 ) is programmed with the deep power-down value. when the lpc18xx wakes up from deep power-down mode, the boot loader configures the pll1 as the clock source running at 72 mhz. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 64 of 1164 nxp semiconductors UM10430 chapter 8: lpc18xx power management controller (pmc) 8.3 register description 8.3.1 hardware sleep event enab le register pd0_sleep0_hw_ena 8.3.2 sleep power mode register pd0_sleep0_mode the pd0_sleep0_mode register controls which of the th ree reduced po wer modes, deep-sleep, power-down, or deep power-down is entered when an arm wfe/wfi instruction is issued and th e sleepdeep bit is set to 1. remark: only the three values listed in table 41 are allowed settings for the pd0_sleep0_mode register. table 39. register overview: power mode controller (pmc) (base address 0x4004 2000) name access address offset description reset value pd0_sleep0_hw_ena r/w 0x000 hardware sleep event enable register 0x0000 0001 - - 0x004 - 0x018 reserved - pd0_sleep0_mode r/w 0x01c sleep power mode register table 40. hardware sleep event enable register (pd0_sleep0_hw_ena - address 0x4004 2000) bit description bit symbol description reset value access 0 ena_event0 writing a 1 enables any sleep modes for cortex-m3. 1 r/w 31:1 - reserved, user software should not write ones to reserved bits. the value read from a reserved bit is not defined. -- table 41. sleep power mode register (p d0_sleep0_mode - address 0x4004 201c) bit description bit symbol description reset value access 31:0 pwr_state selects between deep-sleep, power-down, and deep power-down modes. only one of the following three values can be programmed in this register: 0x003f 00aa = deep-sleep mode 0x003f fcba = power-down mode 0x003f ff7f = deep power-down mode r/w www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 65 of 1164 nxp semiconductors UM10430 chapter 8: lpc18xx power management controller (pmc) 8.4 functional description 8.4.1 run-time programming the pd0_sleep0_mode register can be progra mmed at run-time to change the default power state of the lpc18xx after the next trans ition to a reduced-power state. the default state is deep power-down corresponding to a reset value of the pd0_sleep0_mode register of 0x003f ff7f. [1] when the io pads are off, the external io suppl y should be removed. pin rtc_alarm can be used to indicate when the event router and the core become active and when the io should be powered on. 8.4.2 power api table 42. typical settings for pmc power modes power mode pd0_sleep0_mode register bit settings description deep-sleep 0x0030 00aa cpu, peripherals, analog, usb phy, and retention supplies in retention mode; all sram supplies in active mode; io pads powered [1] , bod in power-down mode. power-down 0x0030 fc3a cpu, peripherals, analog supplies in retention mode; usb phy in power-down mode; retention in retention mode; sram1 in active mode; all other srams in power-down mode; io pads powered [1] , bod in power-down mode. deep power-down 0x0030 ff7f cpu, peripherals, analog, usb phy in power-down mode; all srams, io pads powered [1] , bod in power-down mode. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 66 of 1164 9.1 how to read this chapter remark: this chapter describes the clock generation of parts lpc1850/30/20/10 rev ?a? and parts lpc18xx (with on-chip flash). note that register clocks and clock control registers are specific to parts lpc1850/30/ 20/10 rev ?a? and parts lpc18xx (with on-chip flash). for a description of the cgu of parts lpc1850/30/20/10 rev ?-?, see section 42.4 . ethernet, usb0, usb1, and lcd related clo cks are not available on all packages. see section 1.3 . the corresponding clock control registers are reserved. 9.2 basic configuration the cgu is configured as follows: ? see ta b l e 4 3 for clocking and power control. ? do not reset the cgu during normal operation. 9.3 features ? pll control ? oscillator control ? clock generation and clock source multiplexing ? five integer dividers 9.4 general description the cgu generates multiple independent clocks for the core and the peripheral blocks of the lpc18x. each independent clock is called a ba se clock and itself is one of the inputs to the two clock control units (ccus) which co ntrol the branch clocks to the individual peripherals (see chapter 10 ). UM10430 chapter 9: lpc18xx clock generation unit (cgu) rev. 00.13 ? 20 july 2011 user manual table 43. cgu clocking and power control base clock branch clock maximum frequency cgu base_m3_clk clk_m3_bus 150 mhz www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 67 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) the cgu selects the inputs to the clock generat ors from multiple clock sources, controls the clock generation, and routes the outputs of the clock generators through the clock source bus to the output stages. each output stage provides an independent clock source and corresponds to one of the base clocks for the lpc18xx. see ta b l e 4 4 for a description of each base clock and ta b l e 4 6 for the possible clock sources for each base clock. the cgu contains four types of clock generators: 1. external clock inputs and internal clocks: the external clock inputs are the ethernet phy clocks and the general purpose input clock gp_clkin. the clocks from the internal oscillators are the irc and the 32 khz osc illator output clocks. these clock generators have no selectable inputs from the clock source bus and provide one clock output each to the clock source bus. 2. crystal oscillator: the crystal oscillator is controlled by the cgu. the input to the crystal oscillator are the xtal pins. the crystal oscilla tor creates one output to the clock source bus. 3. plls: pll0 (usb0), pll0 (audio), and pll1 are controlled by the cgu. each pll can select one input from the clock source bus and provides one output to the clock source bus. the input to the plls can be selected from all external and internal clocks and oscillators, from th e other plls, an d from the outputs of any of the integer dividers (see ta b l e 4 5 ). one pll0 cannot select the other pll0 as input. 4. integer dividers: each of the five integer dividers can select one input from the clock source bus and creates one divided output cl ock to the clock source bus. the input to all integer dividers can be selected from all external and internal clocks and oscillators, and from a ll three plls. in addition, the out put of the first integer divider can be selected as an input to all other integer dividers (see ta b l e 4 5 ). fig 17. cgu and ccu0/1 block diagram 32 khz osc pll0 (audio) pll0 (usb0) idiva /4 idivb /16 idive /256 outclk1, 3 - 6, 9 - 10 (base_xxx_clk) outclk12 - 19 (base_xxx_clk) crystal osc pll1 idivc /16 idivc /16 base_safe_clk outclk20 outclk7 outclk8 outclk11 12 mhz irc enet_rx_clk enet_rx_clk enet_tx_clk lcd_clk enet_tx_clk gp_clk 7 8 cgu xtal1 rtcx1 rtcx2 xtal2 ccu1 ccu2 branch clocks to core and peripherals branch clocks to peripherals clkout outclk25 apll outclk26 cgu_out0 outclk27 cgu_out1 wwdt www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 68 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) ? integer divider a: maximum division factor = 4 (see ta b l e 6 2 ). ? integer dividers b, c, d: maximum division factor = 16 (see ta b l e 6 3 ). ? integer divider e: maximum division factor = 256 (see ta b l e 6 4 ). the output stages select a clock source from the clock source bus for each base clock (see table 46 ). except for th e base clocks to the wwdt (base_safe_clk) and usb0 (base_usb0_clk), the clock source for each output stage can be any of the external and internal clocks and oscillato rs directly or one of the pll outputs or any of the outputs of the integer dividers. [1] maximum frequency that guarantees stable operation of the lpc18xx. ta b l e 4 5 shows all available input clock sources for each clock generator. table 44. cgu0 base clocks number name frequency [1] description 0 base_safe_clk 12 mhz base safe clock (always on) for wdt 1 base_usb0_clk 480 mhz base clock for usb0 2- - reserved 3 base_usb1_clk 150 mhz base clock for usb1 4 base_m3_clk 150 mhz system base clock for arm cortex-m3 core and apb peripheral blocks #0 and #2 5 base_spifi_clk 150 mhz base clock for spifi 6 - 150 mhz reserved 7 base_phy_rx_clk 75 mhz base clock for ethernet phy rx 8 base_phy_tx_clk 75 mhz base clock for ethernet phy tx 9 base_apb1_clk 150 mhz base clock for apb peripheral block # 1 10 base_apb3_clk 150 mhz base clock for apb peripheral block # 3 11 base_lcd_clk 150 mhz base clock for lcd 12 base_enet_csr_clk b ase clock for 13 base_sdio_clk 150 mhz base clock for sd/mmc 14 base_ssp0_clk 150 mhz base clock for ssp0 15 base_ssp1_clk 150 mhz base clock for ssp1 16 base_uart0_clk 150 mhz base clock for uart0 17 base_uart1_clk 150 mhz base clock for uart1 18 base_uart2_clk 150 mhz base clock for uart2 19 base_uart3_clk 150 mhz base clock for uart3 20 base_out_clk 150 mhz base clock for clkout pin 21-24 - - reserved 25 base_apll_clk 150 mhz base clock for audio pll 26 base_cgu_out0_clk 150 mhz base cl ock for cgu_out0 clock output 27 base_cgu_out1_clk 150 mhz base cl ock for cgu_out1 clock output www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 69 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) table 45. available clock sources for cl ock generators with selectable inputs clock generators clock sources pll0 (usb) pll0 (audio) pll1 idiva /4 idivb /16 idivc /16 idivd /16 idive /256 32 khz oscillator yes yes yes yes yes yes yes yes irc 12 mhz yes yes yes yes yes yes yes yes enet_rx_clk yes yes yes yes yes yes yes yes enet_tx_clk yes yes yes yes yes yes yes yes gp_clkin yes yes yes yes yes yes yes yes crystal oscillator yes yes yes yes yes yes yes yes pll0 (usb) no no yes yes no no no no pll0 (audio) no no yes yes yes yes yes yes pll1 yes yes no yes yes yes yes yes idiva yes yes yes no yes yes yes yes idivb yes yes yes no no no no no idivc yes yes yes no no no no no idivd yes yes yes no no no no no idive yes yes yes no no no no no table 46. clock sources for output stages output stages (d = default clock source, y = yes (clock source available), n = no (clock source not available)) clock sources base_safe_clk base_usb0_clk base_usb1_clk base_m3_clk base_spifi_clk reserved base_phy_rx_clk base_phy_tx_clk base_apb1_clk base_apb3_clk base_lcd_clk base_enetcsr_clk base_sdio_clk base_ssp0_clk base_ssp1_clk base_uart0_clk base_uart1_clk base_uart2_clk base_uart3_clk base_out_clk base_apll_clk base_cgu_out0_clk base_cgu_out1_clk 32 khz oscillator nnyyyyyyyyyyyyyyyyyyyyy irc 12 mhz dnddddddddddddddddddddd enet_ rx_clk nnyyyyyyyyyyyyyyyyyyyyy enet_ tx_clk nnyyyyyyyyyyyyyyyyyyyyy gp_ clkin nnyyyyyyyyyyyyyyyyyyyyy crystal oscillator nnyyyyyyyyyyyyyyyyyyyyy pll0 (usb) ndynnnnnnnnnnnnnnnnynyy pll0 (audio) nnyyyyyyyyyyyyyyyyyyyyy www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 70 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) pll1 nnyyyyyyyyyyyyyyyyyyyyy idiva nnyyyyyyyyyyyyyyyyyyyyy idivb nnyyyyyyyyyyyyyyyyyyyyy idivc nnyyyyyyyyyyyyyyyyyyyyy idivd nnyyyyyyyyyyyyyyyyyyyyy idive nnyyyyyyyyyyyyyyyyyyyyy table 46. clock sources for output stages output stages (d = default clock source, y = yes (clock source available), n = no (clock source not available)) clock sources base_safe_clk base_usb0_clk base_usb1_clk base_m3_clk base_spifi_clk reserved base_phy_rx_clk base_phy_tx_clk base_apb1_clk base_apb3_clk base_lcd_clk base_enetcsr_clk base_sdio_clk base_ssp0_clk base_ssp1_clk base_uart0_clk base_uart1_clk base_uart2_clk base_uart3_clk base_out_clk base_apll_clk base_cgu_out0_clk base_cgu_out1_clk fig 18. cgu block diagram 32 khz osc pll0 idiva /4 idivb /16 idive /256 outclk_2 - 19 (base_xxx_clk) crystal osc pll1 idivc /16 idivd /16 base_usb0_clk outclk_20 base_safe_clk 12 mhz irc enet_rx_clk enet_tx_clk gp_clkin 18 5 output generators integer dividers plls oscillators, clock inputs xtal1 rtcx1 rtcx2 xtal2 clkout www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 71 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.5 pin description 9.6 register description the register addresses of the cgu are shown in ta b l e 4 8 . remark: the cgu is configured by the boot loader at reset and when waking up from deep power-down to produce a 72 mhz clock us ing pll1. note that this configuration is not reflected in the re set values given in ta b l e 4 8 . table 47. cgu pin description pin name/ function name direction description xtal1 i crystal oscillator input xtal2 o crystal oscillator output rtcx1 i rtc 32 khz oscillator input rtcx2 o rtc 32 khz oscillator output gp_clkin i general purpose input clock enet_tx_clk i ethernet phy transmit clock enet_rx_clk i ethernet phy receive clock clkout o clock output pin cgu_out0 o cgu spare output 0 cgu_out1 o cgu spare output 1 table 48. register overview: cgu (base address 0x4005 0000) name access address offset description reset value - r 0x000 reserved 0x0110 0106 - r 0x004 reserved 0x0010 0500 - r 0x008 reserved 0x1c00 0000 - r 0x00c reserved 0x0000 0000 - - 0x010 reserved - freq_mon r/w 0x014 frequency monitor register 0x0000 0000 xtal_osc_ctrl r/w 0x018 crystal oscillator control register 0x0000 0005 pll0usb_stat r 0x01c pll0 (usb) status register 0x0100 0000 pll0usb_ctrl r/w 0x020 pll0 (usb) control register 0x0100 0003 pll0usb_mdiv r/w 0x024 pll0 (usb) m-divider register 0x05f8 5b6a pll0usb_np_div r/w 0x028 pll0 (usb) n/p-divider register 0x000b 1002 pll0audio_stat r 0x02c pll0 (audio) status register 0x0100 0000 pll0audio_ctrl r/w 0x030 pll0 (audio) control register 0x0100 4003 pll0audio_mdiv r/w 0x034 pll0 (audio) m-divider register 0x05f8 5b6a pll0audio_np_div r/w 0x038 pll0 (audi o) n/p-divider register 0x000b 1002 pllaudio_frac r/w 0x03c pll0 (audio) 0x0020 0000 pll1_stat r 0x040 pll1 status register 0x0100 0000 pll1_ctrl r/w 0x044 pll1 control register 0x0100 0003 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 72 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) idiva_ctrl r/w 0x048 integer divider a control register 0x0100 0000 idivb_ctrl r/w 0x04c integer divider b control register 0x0100 0000 idivc_ctrl r/w 0x050 integer divider c control register 0x0100 0000 idivd_ctrl r/w 0x054 integer divider d control register 0x0100 0000 idive_ctrl r/w 0x058 integer divider e control register 0x0100 0000 outclk_0_ctrl r/w 0x05c output stage 0 control register for base clock base_safe_clk 0x0100 0000 outclk_1_ctrl r/w 0x060 output stage 1 control register for base clock base_usb0_clk 0x0700 0000 - - 0x064 reserved - outclk_3_ctrl r/w 0x068 output stage 3 control register for base clock base_usb1_clk 0x0100 0000 outclk_4_ctrl r/w 0x06c output stage 4 control register for base clock base_m3_clk 0x0100 0000 outclk_5_ctrl r/w 0x070 output stage 5 control register for base clock base_spifi_clk 0x0100 0000 - r/w 0x074 reserved 0x0100 0000 outclk_7_ctrl r/w 0x078 output stage 7 control register for base clock base_phy_rx_clk 0x0100 0000 outclk_8_ctrl r/w 0x07c output stage 8 control register for base clock base_phy_tx_clk 0x0100 0000 outclk_9_ctrl r/w 0x080 output stage 9 control register for base clock base_apb1_clk 0x0100 0000 outclk_10_ctrl r/w 0x084 output stage 10 control register for base clock base_apb3_clk 0x0100 0000 outclk_11_ctrl r/w 0x088 output stage 11 control register for base clock base_lcd_clk 0x0100 0000 outclk_12_ctrl r/w 0x08c output stage 11 control register for base clock base_enet_csr_clk 0x0100 0000 outclk_13_ctrl r/w 0x090 output stage 13 control register for base clock base_sdio_clk 0x0100 0000 outclk_14_ctrl r/w 0x094 output stage 14 control register for base clock base_ssp0_clk 0x0100 0000 outclk_15_ctrl r/w 0x098 output stage 15 control register for base clock base_ssp1_clk 0x0100 0000 outclk_16_ctrl r/w 0x09c output stage 16 control register for base clock base_uart0_clk 0x0100 0000 outclk_17_ctrl r/w 0x0a0 output stage 17 control register for base clock base_uart1_clk 0x0100 0000 outclk_18_ctrl r/w 0x0a4 output stage 18 control register for base clock base_uart2_clk 0x0100 0000 outclk_19_ctrl r/w 0x0a8 output stage 19 control register for base clock base_uart3_clk 0x0100 0000 table 48. register overview: cgu (base address 0x4005 0000) name access address offset description reset value www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 73 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.1 frequency m onitor register the cgu can report the relative frequency of any operating clock. the clock to be measured must be selected by software, while the fixed-frequency irc clock fref is used as the reference frequency. a 14-bit counter then counts the number of cycles of the measured clock that occur dur ing a user-defined number of reference-clock cycles. when the meas bit is set, the measured-clock counter is reset to 0 and counts up, while the 9-bit reference-clock counter is load ed with the value in rcnt and then counts down towards 0. when either counter reaches its te rminal value both counters are disabled and the meas bit is reset to 0. the current values of the counters can then be read out and the selected frequency obtained by the following equation: if rcnt is programmed to a value equal to the core clock frequency in khz and reaches 0 before the fcnt counter saturates, the value stored in fcnt would then show the measured clock?s frequency in khz without the need for any further calculation. note that the accuracy of this measurem ent can be affected by several factors: 1. quantization error is noticeable if the ra tio between the two clo cks is large (e.g. 100 khz vs. 1 khz), because one counter saturates while the other still has only a small count value. 2. due to synchronization, the counters are not started and stopped at exactly the same time. 3. the measured frequency can only be to the same level of precision as the reference frequency. outclk_20_ctrl r/w 0x0ac output stage 20 control register for base clock base_out_clk 0x0100 0000 outclk_21_ctrl to outclk_24_ctrl r/w 0x0b0 to 0x0bc reserved output stages - outclk_25_ctrl r/w 0x0c0 output stage 25 control register for base clock base_apll_clk outclk_26_ctrl r/w 0x0c4 output stage 26 control register for base clock base_cgu_out0_clk outclk_27_ctrl r/w 0x0c8 output stage 27 control register for base clock base_cgu_out1_clk table 48. register overview: cgu (base address 0x4005 0000) name access address offset description reset value fselected qselected qref initial ?? qref final ?? ? ?? ------------------------------------------------------------------------- - fref ? = www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 74 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.2 crystal oscillator control register the register xtal_osc_control contains th e control bits for the crystal oscillator. table 49. freq_mon register (freq_mon, address 0x4005 0014) bit description bit symbol value description reset value access 8:0 rcnt 9-bit reference clock-counter value 0 r/w 22:9 fcnt 14-bit selected clock-counter value 0 r 23 meas measure frequency 0 r/w 0 rcnt and fcnt disabled 1 frequency counters started 28:24 clk_sel clock-source sele ction for the clock to be measured. all other values are reserved. 0r/w 0x00 32 khz oscillator (default) 0x01 irc 0x02 enet_rx_clk 0x03 enet_tx_clk 0x04 gp_clkin 0x05 reserved 0x06 crystal oscillator 0x07 pll0 (usb) 0x08 pll0 (audio) 0x09 pll1 0x0a reserved 0x0b reserved 0x0c idiva 0x0d idivb 0x0e idivc 0x0f idivd 0x10 idive 31:29 - reserved - - table 50. xtal_osc_ctrl register (xta l_osc_ctrl, address 0x4005 0018) bit description bit symbol value description reset value access 0 enable oscillator-pad enable. do not change the bypass and enable bits in one write-action: this will result in unstable device operation! 1r/w 0 enable 1 power-down (default) www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 75 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.3 pll0 (for usb) registers the pll0 provides a dedicated clock to the high-speed usb0 interface and to usb1. see section 9.7.4.5 for instructions on ho w to set up the pll0. 9.6.3.1 pll0 (for usb) status register 9.6.3.2 pll0 (for usb) control register 1 bypass configure crystal operation or external-clock input pin xtal1. do not change the bypass and enable bits in one write-action: this will result in unstable device operation! 0r/w 0 operation with crystal connected (default). 1 bypass mode. use this mode when an external clock source is used instead of a crystal. 2 hf select frequency range 1 r/w 0 oscillator low-frequency mode (crystal or external clock source 1 to 20 mhz). between 15 mhz to 20 mhz, the state of the hf bit is don?t care. 1 oscillator high-frequency m ode; crystal or external clock source 15 to 25 mhz. between 15 mhz to 20 mhz, the state of the hf bit is don?t care (default) 31:3 - reserved - - table 50. xtal_osc_ctrl register (xta l_osc_ctrl, address 0x4005 0018) bit description bit symbol value description reset value access table 51. pll0usb status register (pll0usb_stat, address 0x4005 001c) bit description bit symbol description reset value access 0 lock pll0 lock indicator 0 r 1 fr pll0 free running indicator 0 r 31:2 - reserved - table 52. pll0usb control register (pll0usb_c trl, address 0x4005 0020) bit description bit symbol value description reset value access 0 pd pll0 power down 1 r/w 0 pll0 enabled 1 pll0 powered down 1 bypass input clock bypass control 1 r/w 0 cco clock sent to post-dividers. use this in normal operation. 1 pll0 input clock sent to post-dividers (default). 2 directi pll0 direct input 0 r/w www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 76 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.3.3 pll0 (for usb) m-divider register 3 directo pll0 direct output 0 r/w 4 clken pll0 clock enable 0 r/w 5- reserved - - 6 frm free running mode 0 r/w 7- reserved 0r/w 8 - reserved. reads as zero. do not write one to this register. 0r/w 9 - reserved. reads as zero. do not write one to this register. 0r/w 10 - reserved. reads as zero. do not write one to this register. 0r/w 11 autoblock block clock automatically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 23:12 - reserved - - 28:24 clk_sel clock source se lection. all other values are reserved. 0x01 r/w 0x00 32 khz oscillator 0x01 irc (default) 0x02 enet_rx_clk 0x03 enet_tx_clk 0x04 gp_clkin 0x06 crystal oscillator 0x09 pll1 0x0c idiva 0x0d idivb 0x0e idivc 0x0f idivd 0x10 idive 31:29 - reserved - - table 52. pll0usb control register (pll0usb_c trl, address 0x4005 0020) bit description ?continued bit symbol value description reset value access table 53. pll0usb m-divider register (pll0usb_mdiv, address 0x4005 0024) bit description bit symbol description reset value access 16:0 mdec decoded m-divider coefficient value. select values for the m-divider between 1 and 131071. 0x5b6a r/w www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 77 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.3.4 pll0 (for usb) np-divider register 9.6.4 pll0 (for audio) registers see section 9.7.4.5 for instructions on ho w to set up the pll0. 9.6.4.1 pll0 (for audio) status register 9.6.4.2 pll0 (for audio) control register 21:17 selp bandwidth select p value 11100 r/w 27:22 seli bandwidth select i value 010111 r/w 31:28 selr bandwidth select r value 0000 r/w table 53. pll0usb m-divider register (pll0usb_mdiv, address 0x4005 0024) bit description ?continued bit symbol description reset value access table 54. pll0usb np-divider register (pll0usb_np_div, address 0x4005 0028) bit description bit symbol description reset value access 6:0 pdec decoded p-divider coefficient value 000 0010 r/w 11:7 - reserved - - 21:12 ndec decoded n-divider coefficient value 1011 0001 r/w 31:22 - reserved - - table 55. pll0audio status register (pll 0audio_stat, address 0x4005 002c) bit description bit symbol description reset value access 0 lock pll0 lock indicator 0 r 1 fr pll0 free running indicator 0 r 31:2 - reserved - table 56. pll0audio control register (pll0audio_ctrl, address 0x4005 0030) bit description bit symbol value description reset value access 0 pd pll0 power down 1 r/w 0 pll0 enabled 1 pll0 powered down 1 bypass input clock bypass control 1 r/w 0 cco clock sent to post-dividers. use this in normal operation. 1 pll0 input clock sent to post-dividers (default). www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 78 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 2 directi pll0 direct input 0 r/w 3 directo pll0 direct output 0 r/w 4 clken pll0 clock enable 0 r/w 5- reserved - - 6 frm free running mode 0 r/w 7- reserved 0r/w 8 - reserved. reads as zero. do not write one to this register. 0r/w 9 - reserved. reads as zero. do not write one to this register. 0r/w 10 - reserved. reads as zero. do not write one to this register. 0r/w 11 autoblock block clock automatically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 12 pllfraq_ req fractional pll word write request 0 r/w 13 sel_ext sd modulator bypass 0 r/w 14 mod_pd sd modulator power-down 1 r/w 0 sd modulator enabled 1 sd modulator powered down 23:15 - reserved - - 28:24 clk_sel clock source se lection. all other values are reserved. 0x01 r/w 0x00 32 khz oscillator 0x01 irc (default) 0x02 enet_rx_clk 0x03 enet_tx_clk 0x04 gp_clkin 0x06 crystal oscillator 0x09 pll1 0x0c idiva 0x0d idivb 0x0e idivc 0x0f idivd 0x10 idive 31:29 - reserved - - table 56. pll0audio control register (pll0audio_ctrl, address 0x4005 0030) bit description ?continued bit symbol value description reset value access www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 79 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.4.3 pll0 (for audio) m-divider register 9.6.4.4 pll0 (for audio) np-divider register 9.6.4.5 pll0 (for audio) fractional divider register 9.6.5 pll1 registers the pll1 is used for the co re and all peripheral blocks. 9.6.5.1 pll1 status register table 57. pll0audio m-divider register (p ll0audio_mdiv, address 0x4005 0034) bit description bit symbol description reset value access 16:0 mdec decoded m-divider coefficient value. select values for the m-divider between 1 and 131071. 0x5b6a r/w 21:17 selp bandwidth select p value 11100 r/w 27:22 seli bandwidth select i value 010111 r/w 31:28 selr bandwidth select r value 0000 r/w table 58. pll0 audio np-divider register (p ll0audio_np_div, address 0x4005 0038) bit description bit symbol description reset value access 6:0 pdec decoded p-divider coefficient value 000 0010 r/w 11:7 - reserved - - 21:12 ndec decoded n-divider coefficient value 1011 0001 r/w 31:22 - reserved - - table 59. pll0audio fractional divider regi ster (pll0audio_frac, address 0x4005 003c) bit description bit symbol description reset value access 21:0 pllfract_ctrl pll fractional divider control word 000 0000 r/w 31:22 - reserved - - table 60. pll1 status register (pll1_st at, address 0x4005 0040) bit description bit symbol description reset value access 0 lock pll1 lock indicator 0 r 31:1 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 80 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.5.2 pll1 control register table 61. pll1_ctrl register (pll1_ctrl , address 0x4005 0044) bit description bit symbol value description reset value access 0 pd pll1 power down 1 r/w 0 pll1 enabled 1 pll1 powered down 1 bypass input clock bypass control 1 r/w 0 cco clock sent to post-dividers. use for normal operation. 1 pll1 input clock sent to post-dividers (default). 2 - reserved. do not write one to this bit. 0 r/w 5:3 - reserved. do not write one to these bits. - - 6 fbsel pll feedback select (see figure 20 ? pll1 block diagram ? ). 0r/w 0 cco output is used as feedback divider input clock. 1 pll output clock (clkout) is used as feedback divider input clock. use for normal operation. 7 direct pll direct cco output 0 r/w 0 disabled 1 enabled 9:8 psel[ post-divider division ratio. the value applied is 2xp. 01 r/w 0x0 1 0x1 2 (default) 0x2 4 0x3 8 10 - reserved - - 11 autoblock block clock auto matically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 13:12 nsel pre-divider division ratio 10 r/w 0x0 1 0x1 2 0x2 3 (default) 0x3 4 15:14 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 81 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.6 integer divider register a 23:16 msel feedback-divider division ratio (m) 00000000 = 1 00000001 = 2 ... 11111111 = 256 11000 r/w 27:24 clk_sel clock-source selection. 0x01 r/w 0x00 32 khz oscillator 0x01 irc (default) 0x02 enet_rx_clk 0x03 enet_tx_clk 0x04 gp_clkin 0x05 reserved 0x06 crystal oscillator 0x07 pll0 0x08 reserved 0x09 reserved 0x0a reserved 0x0b idiva 0x0c idivb 0x0d idivc 0x0e idivd 0x0f idive 31:28 - reserved - - table 61. pll1_ctrl register (pll1_ctrl , address 0x4005 0044) bit description ?continued bit symbol value description reset value access table 62. idiva control register (idiva_c trl, address 0x4005 0048) bit description bit symbol value description reset value access 0 pd integer divider a power down 0 r/w 0 idiva enabled (default) 1 power-down 1- reserved - - 3:2 idiv integer divider a divider values (1/(idiv + 1)) 00 r/w 0x0 1 (default) 0x1 2 0x2 3 0x3 4 10:4 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 82 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.7 integer divider register b, c, d 11 autoblock block clock automatically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 23:12 - reserved - - 28:24 clk_sel clock source selection. all other values are reserved. 0x01 r/w 0x00 32 khz oscillator 0x01 irc (default) 0x02 enet_rx_clk 0x03 enet_tx_clk 0x04 gp_clkin 0x06 crystal oscillator 0x07 pll0 (for usb) 0x08 pll0 (for audio) 0x09 pll1 31:29 - reserved - - table 62. idiva control register (idiva_c trl, address 0x4005 0048) bit description ?continued bit symbol value description reset value access table 63. idivb/c/d control re gisters (idivb_ctrl, address 0x4005 004c; idivc_ctrl, address 0x4005 0050; idivc_ctrl, address 0x4005 0054) bit description bit symbol value description reset value access 0 pd integer divider power down 0 r/w 0 idiv enabled (default) 1 power-down 1- reserved -- 5:2 idiv integer divider b, c, d divider values (1/(idiv + 1)) 0000 = 1 (default) 0001 = 2 ... 1111 = 16 0000 r/w 10:6 - reserved - - 11 autoblock block clock automa tically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 23:12 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 83 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.8 integer divider register e 28:24 clk_sel clock-source selection. all other values are reserved. 0x01 r/w 0x00 32 khz oscillator 0x01 irc (default) 0x02 enet_rx_clk 0x03 enet_tx_clk 0x04 gp_clkin 0x06 crystal oscillator 0x08 pll0 (for audio) 0x09 pll1 0x0c idiva 31:29 - reserved - - table 63. idivb/c/d control re gisters (idivb_ctrl, address 0x4005 004c; idivc_ctrl, address 0x4005 0050; idivc_ctrl, address 0x4005 0054) bit description bit symbol value description reset value access table 64. idive control regist er (idive_ctrl, address 0x4005 0058) bit description bit symbol value description reset value access 0 pd integer divider power down 0 r/w 0 idiv enabled (default) 1 power-down 1- reserved - - 9:2 idiv integer divider e divider values (1/(idiv + 1)) 00000000 = 1 (default) 00000001 = 2 ... 111111111 = 256 000000 00 r/w 10 - reserved - - 11 autoblock block clock automatically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 23:12 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 84 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.9 output stage 0 control register this register controls the base_safe_clk to the watchdog os cillator. the only possible clock source for this base clock is the irc. 9.6.10 output stage 1 control register this register contro ls the base_usb0_clk to the high- speed usb0. the only possible clock source for this base cl ock is the pll0 (usb) output. 27:24 clk_sel clock-source selection. all other values are reserved. 0x01 r/w 0x00 32 khz oscillator 0x01 irc (default) 0x02 enet_rx_clk 0x03 enet_tx_clk 0x04 gp_clkin 0x06 crystal oscillator 0x08 pll0 (for audio) 0x09 pll1 0x0c idiva 31:28 - reserved - - table 64. idive control regist er (idive_ctrl, address 0x4005 0058) bit description bit symbol value description reset value access table 65. output stage 0 control register (outclk_0_ctrl, address 0x4005 005c) bit description bit symbol value description reset value access 0 pd output stage power down 0 r/w 0 output stage enabled (default) 1 power-down 10:1 - reserved - - 11 autoblock block clock automatically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 23:12 - reserved - - 28:24 clk_sel clock source selection. all other values are reserved. 0x01 r/w 0x01 irc (default) 31:29 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 85 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.11 output stage 3 control register these registers control base clocks 3 (usb1). table 66. output stage 1 control register (outclk_1_ctrl, address 0x4005 0060) bit description bit symbol value description reset value access 0 pd output stage power down 0 r/w 0 output stage enabled (default) 1 power-down 10:1 - reserved - - 11 autoblock block clock auto matically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 23:12 - reserved - - 28:24 clk_sel clock-source selection. 0x07 r/w 0x07 pll0 (for usb, default) 31:29 - reserved - - table 67. output stage 3 control register (outclk_3_ctrl, address 0x4005 0068) bit description bit symbol value description reset value access 0 pd output stage power down 0 r/w 0 output stage enabled (default) 1 power-down 10:1 - reserved - - 11 autoblock block clock automatically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 23:12 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 86 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.12 output stage 4 to 19 control registers these registers control base clocks 4 to 19. 28:24 clk_sel clock source selection. all other values are reserved. 0x01 r/w 0x00 32 khz oscillator 0x01 irc (default) 0x02 enet_rx_clk 0x03 enet_tx_clk 0x04 gp_clkin 0x06 crystal oscillator 0x07 pll0 (for usb) 0x08 pll0 (for audio) 0x09 pll1 0x0c idiva 0x0d idivb 0x0e idivc 0x0f idivd 0x10 idive 31:29 - reserved - - table 67. output stage 3 control register (outclk_3_ctrl, address 0x4005 0068) bit description ?continued bit symbol value description reset value access table 68. output stage 4 to 19 control registers (outclk_4_ctrl to outclk_19_ctrl, address 0x4005 006c to 0x4005 00a8) bit description bit symbol value description reset value access 0 pd output stage power down 0 r/w 0 output stage enabled (default) 1 power-down 10:1 - reserved - - 11 autoblock block clock automatically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 23:12 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 87 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.13 output stage 20 register this register controls the clock output to t he clkout pin. all clock generator outputs can be monitored through this pin. 28:24 clk_sel clock source selection. all other values are reserved. 0x01 r/w 0x00 32 khz oscillator 0x01 irc (default) 0x02 enet_rx_clk 0x03 enet_tx_clk 0x04 gp_clkin 0x06 crystal oscillator 0x08 pll0 (for audio) 0x09 pll1 0x0c idiva 0x0d idivb 0x0e idivc 0x0f idivd 0x10 idive 31:29 - reserved - - table 68. output stage 4 to 19 control registers (outclk_4_ctrl to outclk_19_ctrl, address 0x4005 006c to 0x4005 00a8) bit description ?continued bit symbol value description reset value access table 69. output stage 20 control register (outclk_20_ctrl, addresses 0x4005 00ac) bit description bit symbol value description reset value access 0 pd output stage power down 0 r/w 0 output stage enabled (default) 1 power-down 10:1 - reserved - - 11 autoblock block clock automatically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 23:12 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 88 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.14 output stage 25 register this register controls the clock output to the . 27:24 clk_sel clock-source selection. 0x01 r/w 0x00 32 khz oscillator 0x01 irc (default) 0x02 enet_rx_clk 0x03 enet_tx_clk 0x04 gp_clkin 0x05 reserved 0x06 crystal oscillator 0x07 pll0 (for usb) 0x08 pll0 (for audio) 0x09 pll1 0x0c idiva 0x0d idivb 0x0e idivc 0x0f idivd 0x10 idive 31:28 - reserved - - table 69. output stage 20 control register (outclk_20_ctrl, addresses 0x4005 00ac) bit description ?continued bit symbol value description reset value access table 70. output stage 25 control register (outclk_25_ctrl, addresses 0x4005 00c0) bit description bit symbol value description reset value access 0 pd output stage power down 0 r/w 0 output stage enabled (default) 1 power-down 10:1 - reserved - - 11 autoblock block clock automatically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 23:12 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 89 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.6.15 output stage 26 to 27 register this register controls the clock output to the spare cgu outputs pins cgu_out0 and cgu_out1. all clock generator outputs can be monitored through this pin. 27:24 clk_sel clock-source selection. 0x01 r/w 0x00 32 khz oscillator 0x01 irc (default) 0x02 enet_rx_clk 0x03 enet_tx_clk 0x04 gp_clkin 0x05 reserved 0x06 crystal oscillator 0x07 reserved 0x08 pll0 (for audio) 0x09 pll1 0x0c idiva 0x0d idivb 0x0e idivc 0x0f idivd 0x10 idive 31:28 - reserved - - table 70. output stage 25 control register (outclk_25_ctrl, addresses 0x4005 00c0) bit description ?continued bit symbol value description reset value access table 71. output stage 26 to 27 control register (outclk_26_ctrl to outclk_27_ctrl, addresses 0x4005 00c4 to 0x4005 00c8) bit description bit symbol value description reset value access 0 pd output stage power down 0 r/w 0 output stage enabled (default) 1 power-down 10:1 - reserved - - 11 autoblock block clock automatically during frequency change 0r/w 0 autoblocking disabled 1 autoblocking enabled 23:12 - reserved - - www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 90 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.7 functional description 9.7.1 32 khz oscillator the 32 khz oscillator output is controlled by the creg block (see ta b l e 3 1 ). the rtc and the alarm timer are connected directly to the 32 khz oscillator. 9.7.2 irc the irc is a trimmed 12 mhz internal oscillato r. although it's part of the cgu, the cgu has no control over this clock source. the irc is put into power down depending on the power saving mode. 9.7.3 crystal oscillator the crystal oscillator is controlled by t he xtal_osc_ctrl register in the cgu (see ta b l e 5 0 ). 9.7.4 pll0 (for usb and audio) 9.7.4.1 features ? input frequency: 14 khz to 150 mhz. the inpu t from an external crystal is limited to 25 mhz. ? cco frequency: 275 mhz to 550 mhz. 27:24 clk_sel clock-source selection. 0x01 r/w 0x00 32 khz oscillator 0x01 irc (default) 0x02 enet_rx_clk 0x03 enet_tx_clk 0x04 gp_clkin 0x05 reserved 0x06 crystal oscillator 0x07 pll0 (for usb) 0x08 pll0 (for audio) 0x09 pll1 0x0c idiva 0x0d idivb 0x0e idivc 0x0f idivd 0x10 idive 31:28 - reserved - - table 71. output stage 26 to 27 control register (outclk_26_ctrl to outclk_27_ctrl, addresses 0x4005 00c4 to 0x4005 00c8) bit description ?continued bit symbol value description reset value access www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 91 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) ? output clock range: 4.3 mhz to 550 mhz. ? programmable dividers: ? pre-divider n (n, 1 to 2 8 ) ? feedback-divider 2 x m (m, 1 to 2 15 ) ? post-divider p x 2 (p, 1 to 2 5 ). ? programmable bandwidth (integrating acti on, proportional action, high frequency pole). ? on-the-fly adjustment of the clock possi ble (dividers with handshake control). ? positive edge clocking. ? frequency limiter to avoid hang-up of the pll. ? lock detector. ? power-down mode. ? free running mode remark: both pll0 blocks are functionally identic al. the pll0 for audio applications (pll0 for audio) supports an additional fractional divider stage (see section 9.7.5 ). 9.7.4.2 pll0 description the block diagram of the pll is shown in figure 19 . the clock input has to be fed to pin clkin. pin clkout is the pll clock output. the analog part of the pll consists of a phase frequency detector (pfd), f ilter and a current controlled oscillator (cco). the pfd has two inputs, a reference input from the (divided) external clock and one input from the divided cco output clock. the pfd compares the phase/frequency of these input signals and generates a control signal if they don?t ma tch. this control signal is fed to a filter which drives the cco. the pll contains three programmable dividers: pre-divider (n), feedback-divider (m) and post-divider (p). the pll contains a lock det ector which measures the phase difference between the rising edges of the input and feedba ck clocks. only when this difference is fig 19. pll0 block diagram bypass pll0_ctrl [1] clkout clkin 32khz irc enet_rx_clk enet_tx_clk gp_clkin crystal pll1 idiva idivb idivc idivd idive pll0_ctrl[27:24] ?1? n-divider pll0 npdiv [ 21:12 ] direct input pll0_ctrl[2] pfd filter cco q d clken pll0_ctrl[4] /2 pll0_npdiv[6:0] p-divider /2 m-divider pll0_mdiv[16:0] direct output pll0_ctrl [3] bandwidth select p,i,r pll0_mdiv[31:17] www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 92 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) smaller than the so called ?lock criterion? for more than seven consecutive input clock periods, the lock output switches from low to high. a single too large phase difference immediately resets the counter and causes the lock signal to drop (if it was high). requiring seven phase measurements in a row to be below a certain figure ensures that the lock detector will not indicate lock until both the phase and freque ncy of the input and feedback clocks are very well aligned. this ef fectively prevents false lock indications, and thus ensures a glitch free lock signal. to avoid frequency hang-up the pll contains a frequency limiter. this feature is built in to prevent the cco from running too fast, this ca n occur if e.g. a wrong feedback-divider (m) ratio is applied to the pll. 9.7.4.3 use of pll0 operating modes 9.7.4.3.1 normal mode mode 1 is the normal operating mode. the pre- and post-divider can be selected to give: ? mode 1a: normal operating mode without post-divider and without pre-divider ? mode 1b: normal operating mode with post-divider and without pre-divider ? mode 1c: normal operating mode without post-divider and with pre-divider ? mode 1d: normal operating mode with post-divider and with pre-divider to get at the output of the pll (clkout) the best phase-noise and jitter performance, the highest possible reference clock (clkref) at the pfd has to be used. therefore mode 1a and 1b are recommended, when it is possible to make the right output frequency without pre-divider. by using the post-divider the clock at the out put of the pll (clkout) the divider ratio is always even because the divide-by-2 divider after the post-divider. 9.7.4.3.2 mode 1a: normal operating mode without post-divider and without pre-divider in normal operating mode 1a the post-divider and pre-divider are bypassed. the operating frequencies are: table 72. pll operating modes pll0_mode bit settings: mode pd clken bypass directi directo frm 1: normal 0 1 0 1/0 1/0 0 3: power down 1 x x x x x table 73. directl and directo bit settings in hp0/1_mode register mode directi directo 1a 1 1 1b 1 0 1c 0 1 1d 0 0 www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 93 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) fout = fcco = 2 x m x fin ?? (275 mhz ? fcco ? 550 mhz, 4 khz ? fin ? 150 mhz) the feedback divider ratio is programmable: ? feedback-divider m (m, 1 to 2 15 ) 9.7.4.3.3 mode 1b: normal operating mode with post-divider and without pre-divider in normal operating mode 1b the pre-divider is bypassed. the operating frequencies are: fout = fcco /(2 x p) = (m / p) x fin ? (275 mhz ? fcco ? 550 mhz, 4 khz ? fin ? 150 mhz) the divider ratios are programmable: ? feedback-divider m (m, 1 to 2 15 ) ? post-divider p (p, 1 to 32) 9.7.4.3.4 mode 1c: normal operating mode without post-divider and with pre-divider in normal operating mode 1c the post-divider with divide-by-2 divider is bypassed. the operating frequencies are: fout = fcco = 2 x m x fin / n ? (275 mhz ? fcco ? 550 mhz, 4 khz ? fin/n ? 150 mhz) the divider ratios are programmable: ? pre-divider n (n, 1 to 256) ? feedback-divider m (m, 1 to 2 15 ) 9.7.4.3.5 mode 1d: normal operating mode with post-divider and with pre-divider in normal operating mode 1d none of the dividers are bypassed. the operating frequencies are: fout = fcco /(2 x p) = m x fin /(n x p) ? (275 mhz ? fcco ? 550 mhz, 4 khz ? fin/n ? 150 mhz) the divider ratios are programmable: ? pre-divider n (n, 1 to 256) ? feedback-divider m (m, 1 to 2 15 ) ? post-divider p (p, 1 to 32) 9.7.4.3.6 mode 3: power down mode (pd) in this mode (pd = '1'), the oscillator will be st opped, the lock output will be made low, and the internal current refe rence will be turned off. during pd it is also possible to load new divider ratios at the input buses (msel, psel, nsel). power-down mode is ended by making pd low, causing the pll to start up. the lock signal will be made hi gh once the pll has regained lock on the input clock. 9.7.4.4 settings for usb0 ta b l e 7 4 shows the divider settings used for co nfiguring a certain output frequency f out for usb0. www.datasheet.co.kr datasheet pdf - http://www..net/
draft draft draft dr draft draft draft d raf draft draft dra f t d raft dr aft d dra f t draft draft d raft draft d raft dra all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. user manual rev. 00.13 ? 20 july 2011 94 of 1164 nxp semiconductors UM10430 chapter 9: lpc18xx cloc k generation unit (cgu) 9.7.4.5 usage notes in order to set up the pll0, follow these steps: 1. power down the pll0 by setting bit 1 in the pll0_ctrl register to 1. this step is only needed if the pll0 is currently enabled. 2. configure the pll0 m, n, and p divider values in the pll0_m and pll0_np registers. 3. power up the pll0 by setting bit 1 in the pll0_ctrl register to 0. 4. wait for the pll0 to lock by monitoring the lock bit in the pll0_stat register. 5. enable the pll0 clock output in the pll0_ctrl register. 9.7.5 fractional divider fo r the pll0 (for audio) the pll0 for audio applications (pll0 (for audio)) includes an additional fractional divider. 9.7.6 pll1 9.7.6.1 features ? 1 mhz to 50 mhz input frequency. the input from an external crystal is limited to 25 mhz. ? 9.75 mhz to 320 mhz selectable output frequency with 50% duty cycle. ? 156 mhz to 320 mhz current cont rolled oscillator (cco) frequency. ? power-down mode. ? lock detector. table 74. system pll divider ratio settings for 12 mhz fout (mhz) fcco (mhz) ndec mdec pdec selr seli selp |
